XRT94L33IB-L Exar Corporation, XRT94L33IB-L Datasheet - Page 150

• Manufacturer Part Number: XRT94L33IB-L
• Description: IC MAPPER DS3/E3/STS-1 504TBGA
• Manufacturer: Exar Corporation

Specifications of XRT94L33IB-L

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 3.14 V ~ 3.47 V
• Package / Case: 504-LBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

XRT94L33
Rev.1.2.0.
2.2
If a given channel (or the entire device) is configured to operate in the ATM Mode, then the purpose of the
Transmit section within the XRT94L33 1-Channel STS-3c/STS-3 ATM UNI device is to allow a local ATM
Layer (or ATM Adaptation Layer) processor to transmit ATM Cell data to a remote piece of equipment via an
OC-3c or OC-3 transport medium
For ATM UNI Applications, the Transmit Section of the XRT94L33 chip consists of the following functional
blocks:
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The ATM Layer processor will write ATM Cell Data to the Transmit UTOPIA Interface Block of the XRT94L33.
The Transmit UTOPIA Interface block provides the industry standard ATM/PHY interface functions. The
Transmit UTOPIA Interface Block will ultimately write this cell data to an internal FIFO (referred to as TxFIFO
throughout this document); where it can be read and further processed by the Transmit ATM Cell Processor
Block. The Transmit UTOPIA Interface block will also provide signaling to support data-flow control between
the ATM Layer Processor and the Transmit UTOPIA Interface block.
The Transmit ATM Cell Processor block will read in the ATM cell data from the TxFIFO. As the Transmit ATM
Cell Processor block reads in this ATM cell data (from the Tx FIFO) it will perform some parity checking on
this data. If the Transmit ATM Cell Processor block detects any parity errors in these incoming ATM cells,
then these ATM cells are optionally discarded.
processed by a “user-defined” (e.g., “Transmit User”) cell filter. All cells (with header bytes) that do not
comply with the “user-defined” filtering requirements will be (optionally) discarded. Additionally, this Transmit
User Cell Filter can be configured to copy and route “replicate” cells (that contain “header-byte” patterns that
match the “User-defined” Cell Filtering criteria) to the “Transmit Cell Extraction” Buffer/Processor where these
ATM cells can be read out and processed via the Microprocessor Interface. Continuing along the transmit
output path, the Transmit ATM Cell Processor block will then (optionally) proceed to take the first four octets
of a given cell and compute the HEC (Header Error Check) byte from these bytes. Afterwards the Transmit
ATM Cell Processor block will insert this HEC byte into the 5th octet position within the cell. The Transmit
ATM Cell Processor block will also (optionally) scramble the payload portion of the cell (bytes 6 through 53) in
order to prevent user data from mimicking framing or control bits/bytes. Once the cell has gone through this
process it will then be transferred to either of the Transmit STS-3c POH Processor block or the corresponding
Transmit SONET POH Processor blocks for further processing.
If the TxFIFO (within the Transmit UTOPIA Interface block) is depleted and has no (user) cells available, then
the Transmit ATM Cell Processor block will automatically read out the contents of all cells residing within the
“Transmit Cell Insertion” Buffer, and will transmit these cells into the outbound ATM cell traffic via the
“Transmit Data Path”. Once the “Transmit Cell Insertion Buffer” has been depleted, then the Transmit ATM
Cell Processor block will generate, process and transmit Idle cells, in the exact same manner as with user
cells. This generation and transmission of Idle cells is also known as cell-rate decoupling (e.g., Idle cells are
generated in order to fill up the bandwidth of the PMD carrier requirements – 155.52 Mbps in this case). The
Transmit ATM Cell Processor block has provisions to allow the user to generate and transmit certain “user-
defined” cells, such as OAM cells via the “Transmit Cell Insertion” Processor block.
Note:
Transmit UTOPIA Interface Block
Transmit ATM Cell Processor Block
Transmit STS-3c POH Processor Block (for STS-3c Applications)
Transmit SONET POH Processor Block (for STS-3 Applications)
Transmit STS-3 TOH Processor Block
THE TRANSMIT DIRECTION
These special or OAM cells will be subjected to the same processing as are User and Idle cells (e.g., HEC Byte
Calculation and Insertion, Cell Payload Scrambling).
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
Afterwards, all “error-free” ATM cell data will then be
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