XRT94L33IB-L Exar Corporation, XRT94L33IB-L Datasheet - Page 373

• Manufacturer Part Number: XRT94L33IB-L
• Description: IC MAPPER DS3/E3/STS-1 504TBGA
• Manufacturer: Exar Corporation

Specifications of XRT94L33IB-L

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 3.14 V ~ 3.47 V
• Package / Case: 504-LBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

xr
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
•
Transport – B2 Error Count” Registers.
The Relationship between the “Overall” SF Condition, and the States of the “Interval” and “Burst”
Detectors
The “SF Condition” (as declared and cleared by the Receive STS-3 TOH Processor block) is the “logical OR”
of the “SF Declaration” state of the “Interval” and “Burst” SF Detector.
In other words, the Receive STS-3 TOH Processor block will declare the SF condition, if either the “Interval”
or the “Burst” SF Detector are currently declaring the “SF Condition”.
The operation of the “Interval” and “Burst” SF Detectors are both described in detail below.
2.3.1.14.2
In this case, the user specifies three parameters to define the SF Declaration criteria.
• The minimum number of B2 errors (e.g., a B2 error-threshold) accumulated over a given “SF Set Interval”
time period.
• The length (in terms of SONET frame periods) of this “SF Set Interval” time period.
Once the user defines these parameters, then the Receive STS-3 TOH Processor block will begin to count
the cumulative number of B2 errors that it detects within a “sliding window” of time. The length of this “sliding
window of time” is dictated by the user-defined “SF Set Interval” time period.
As long as the Receive STS-3 TOH Processor block does not detect the “B2 error-threshold” number of B2
errors, within this “SF Set Interval” of time, then it will not declare the SF Condition. Conversely, if the
Receive STS-3c TOH Processor block detects at least the “B2 error threshold” number of B2 errors, within the
“SF Set Interval” of time, then it will declare the SF Condition.
S
The user can specify the “B2 Error Threshold” by writing the appropriate value into the “Receive STS-3
Transport – Receive SF Set Threshold – Byte 1 and Byte 0” registers, as depicted below.
Receive STS-3 Transport – Receive SF SET Threshold – Byte 1 (Address = 0x1136)
Receive STS-3 Transport – Receive SF SET Threshold – Byte 0 (Address = 0x1137)
Notes:
The “Receive STS-3 Transport – Receive SF SET Threshold – Byte 1 and Byte 0” Registers permits the user to write in a
The “default” value for the “B2 Error Threshold” is 0xFFFF.
S
Likewise, the user can specify the “SF Set Interval” period by writing the appropriate value into the “Receive
STS-3 Transport – Receive SF Set Monitor Interval – Byte 2, 1 and 0” registers, as depicted below.
PECIFYING THE
PECIFYING THE
The amount by which the Receive STS-3 TOH Processor block will increment the “Receive STS-3
B
B
R/W
R/W
16-bit expression for the “B2 Error Threshold”.
IT
IT
1
1
7
7
The SF (Signal Fail) Defect Declaration Criteria
“B2 E
“SF S
B
B
R/W
R/W
IT
IT
1
1
6
6
RROR
ET
I
NTERVAL
T
HRESHOLD
B
B
R/W
R/W
IT
IT
1
1
”
5
5
OF
T
”
IME
FOR
SF_SET_THRESHOLD[15:8]
SF_SET_THRESHOLD[7:0]
D
B
B
R/W
R/W
ECLARING
IT
IT
1
1
4
4
373
SF
B
B
R/W
R/W
IT
IT
1
1
3
3
B
B
R/W
R/W
IT
IT
1
1
2
2
B
B
R/W
R/W
IT
IT
1
1
1
1
XRT94L33
Rev.1.2.0.
B
B
R/W
R/W
IT
IT
1
1
0
0