XRT94L33IB-L Exar Corporation, XRT94L33IB-L Datasheet - Page 358

• Manufacturer Part Number: XRT94L33IB-L
• Description: IC MAPPER DS3/E3/STS-1 504TBGA
• Manufacturer: Exar Corporation

Specifications of XRT94L33IB-L

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 3.14 V ~ 3.47 V
• Package / Case: 504-LBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

XRT94L33
Rev.1.2.0.
2.3.1.6.2
The user can also configure the Receive STS-3 TOH Processor block to increment the “Receive STS-3
Transport – REI-L Error Count” Register, by the value “1” for each STS-3 frame that contains a “non-zero”
REI-L value.
The user can implement this configuration by setting Bit 2 (REI-L Error Type), within the “Receive STS-3
Transport – Control Register – Byte 0” to “1”, as illustrated below.
Receive STS-3 Transport Control Register – Byte 0 (Address = 0x1103)
2.3.1.6.3
2.3.1.7
2.3.1.8
2.3.1.9
2.3.1.10
2.3.1.11
The Receive STS-3 TOH Processor Block has the responsibility for computing and verifying the Section BIP-8
(e.g., B1) byte within each incoming STS-3 frame. When the Receive STS-3 TOH Processor block executes
this function, it will do the following.
•
•
•
If the Receive STS-3 TOH Processor block detects any B1 byte errors, then it will do the following.
Receive STS-3 Transport Interrupt Status Register – Byte 0 (Address = 0x110B)
Change of
SF Defect
Condition
Interrupt
Unused
Status
B
B
RUR
R/O
It will read in the contents of a given “newly received” STS-3 frame.
It will compute the BIP-8 value of this entire STS-3 frame.
This resulting BIP-8 value will be compared with the contents of the B1 byte, within the very next “newly
received” STS-3 frame.
IT
IT
0
0
7
7
RECEIVE SECTION TRACE MESSAGES VIA THE INCOMING J0 BYTE
HANDLING/SUPPORT OF THE INCOMING E1 BYTE
HANDLING/SUPPORT OF THE INCOMING F1 BYTE
HANDLING/SUPPORT OF THE INCOMING SECTION DCC (D1, D2 AND D3) BYTES
SECTION BIP-8 (B1) BYTE VERIFICATION
o
Configuring the Receive STS-3 TOH Processor block to increment the “Receive STS-3
Transport – REI-L Error Count” Register on a “per STS-3 Frame” basis.
Reading out the contents of the “Receive STS-3 Transport – REI-L Error Count Registers,
during Performance Monitoring
Change of
SF Detect
SD Defect
Condition
Interrupt
It will generate the “Detection of B1 Byte Error” Interrupt, by toggling the “INT*” output pin
“LOW” and by setting Bit 3 (Detection of B1 Byte Error Interrupt Status) within the “Receive
STS-3 Transport Interrupt Status” Register to “1”, as indicated below.
Enable
Status
B
B
RUR
R/W
IT
0
IT
0
6
6
Detection of
REI-L Error
SD Detect
Interrupt
Enable
Status
B
R/W
B
RUR
IT
0
IT
0
5
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
5
Detection of
Descramble
Interrupt
B2 Byte
Disable
Status
B
Error
B
RUR
R/W
IT
IT
0
0
4
4
358
Detection of
Interrupt
B1 Byte
SONET*
Status
B
Error
RUR
SDH/
B
R/W
IT
1
IT
0
3
3
LOF Defect
Change of
Error Type
Condition
Interrupt
Status
REI-L
B
RUR
B
R/W
IT
IT
0
1
2
2
SEF Defect
Change of
Condition
Interrupt
B2 Error
Status
B
RUR
B
Type
R/W
IT
IT
0
0
1
xr
1
LOS Defect
Change of
Condition
Interrupt
B1 Error
Status
B
Type
B
RUR
R/W
IT
IT
0
0
0
0