XRT94L33IB-L Exar Corporation, XRT94L33IB-L Datasheet - Page 277

• Manufacturer Part Number: XRT94L33IB-L
• Description: IC MAPPER DS3/E3/STS-1 504TBGA
• Manufacturer: Exar Corporation

Specifications of XRT94L33IB-L

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 3.14 V ~ 3.47 V
• Package / Case: 504-LBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

xr
XRT94L33
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
Rev.1.2.0.
Figure 50) is “dashed” because controlling this signal is not necessary if the user has executed “STEP 1” above.
• Whenever the “external circuit” samples both the “TxPOHEnable_n” and “TxPOHFrame_n” output pins
“high”, then it should enter a “WAIT STATE” (e.g., where it will wait for 16 periods of “TxPOHClk_n” to
elapse). Afterwards, the external circuit should exit this “WAIT STATE” and then place the very first bit (e.g.,
the most significant bit) of the “outbound” C2 byte onto the “TxPOH_n” input pin, upon the very next falling
edge of “TxPOHClk_n”. This data bit will be sampled and latched into the “Transmit SONET POH Processor”
block circuitry, upon the very next rising edge of “TxPOHClk_n”.
Note:
This “WAIT STATE” period is necessary because the C2 byte is the third byte within the POH.
• Afterwards, the “external circuit” should serially place the remaining seven bits (of the C2 byte) onto the
“TxPOH_n” input pin, upon each of the next seven falling edges of “TxPOHClk_n”.
• The “external circuit” should then revert back to continuously sampling the states of the “TxPOHEnable_n”
and “TxPOHFrame_n” output pins and repeat the above-mentioned process.
Figure 51 presents an illustration of the “TxPOH Input Interface” waveforms, when the “external circuit” is
writing the C2 byte into the “TxPOH Input Port”.
Figure 51 Illustration of the “TxPOH Input Interface” waveforms, when the “External Circuit” is writing
the “C2 byte” into the “TxPOH Input Port”.
2.2.8.3.6
SUPPORT/HANDLING OF THE F2 BYTE
The Transmit SONET POH Processor block permits the user to control the value of the F2 byte by either of
the following options.
• Setting and controlling the “outbound” F2 Byte via Software
• Setting and controlling the “outbound” F2 Byte via the “TxPOH Input Port”
The details and instructions for using either or these features are presented below.
2.2.8.3.6.1
Setting and Controlling the Outbound F2 Byte via Software
The Transmit SONET POH Processor block permits the user to specify the contents of the F2 byte, within the
“outbound” STS-1 SPE via software command.
The user can configure the Transmit SONET POH Processor block to accomplish this by performing the
following steps.
STEP 1 – Write the value “0” into Bit 7 (F2 Insertion Type) within the “Transmit SONET Path – SONET
Control Register – Byte 0”, as depicted below.
Transmit SONET Path – SONET Control Register – Byte 0 (Address = 0xN983)
B
7
B
6
B
5
B
4
B
3
B
2
B
1
B
0
IT
IT
IT
IT
IT
IT
IT
IT
F2 Insertion
REI-P Insertion Type[1:0]
RDI-P Insertion Type[1:0]
C2 Byte
Unused
Transmit
Type
Insertion
AIS-P
Type
Enable
R/W
R/W
R/W
R/W
R/W
R/W
R/O
R/W
0
0
0
0
0
0
0
0
This step configures the Transmit SONET POH Processor block to read out the contents of the “Transmit
SONET Path – Transmit F2 Byte Value” register; and load this value into the F2 byte position within each
“outbound” STS-1 SPE.
STEP 2 – Write the desired byte value (for the outbound F2 byte) into the “Transmit SONET Path –
Transmit F2 Byte Value” register.
The bit-format of this register is presented below.
277