XRT94L33IB-L Exar Corporation, XRT94L33IB-L Datasheet - Page 129

• Manufacturer Part Number: XRT94L33IB-L
• Description: IC MAPPER DS3/E3/STS-1 504TBGA
• Manufacturer: Exar Corporation

Specifications of XRT94L33IB-L

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 3.14 V ~ 3.47 V
• Package / Case: 504-LBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

xr
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
1.3.2.2
As mentioned earlier, the Microprocessor Interface block supports data transfer between the XRT94L33 and
the µC/µP (e.g., “Read” and “Write” operations) via two modes: the “Programmed I/O” and the “Burst” Modes.
Programmed I/O access is discussed within this revision of the data sheet. Burst Mode access will be
discussed in the next revision of this data sheet.
1.3.2.3
“Programmed I/O” is the conventional manner in which a microprocessor exchanges data with a peripheral
device. However, it is also the slowest method of data exchange between the XRT94L33 and the µC/µP; as
will be described in this text.
The next two sections present detailed information on Programmed I/O Access, when the XRT94L33 is
operating in the “Intel Mode” and in the “Motorola Mode”.
1.3.3
If the XRT94L33 is interfaced to an “Intel-type” µC/µP (e.g., the 80x86 family, etc.), then it should be
configured to operate in the “Intel” mode (by tying the “MOTO” pin to ground). Intel-type “Read” and “Write”
operations are described below.
1.3.3.1
Whenever an Intel-type µC/µP wishes to read the contents of a register or some location within the Transmit
or Receive Extraction Memory or the J0/J1 Message Buffers, within the XRT94L33, it should do the following.
1. Place the address of the “target” register or buffer location (within the UNI) on the Address Bus input pins
A[14:0].
2. While the µC/µP is placing this address value on the Address Bus, the Address Decoding circuitry (within
the user’s system) should assert the CS* (Chip Select) pin of the XRT94L33, by toggling it “low”. This action
enables further communication between the µC/µP and the XRT94L33 Microprocessor Interface block.
3. Toggle the ALE_AS (Address Latch Enable) input pin “high”. This step enables the “Address Bus” input
drivers, within the Microprocessor Interface block of the XRT94L33.
4. After allowing the data on the Address Bus pins to settle (by waiting the appropriate “Address” Data Setup
time”), the µC/µP should toggle the ALE_AS pin “low”. This step causes the XRT94L33 to “latch” the contents
of the “Address Bus” into its internal circuitry. At this point, the address of the register or buffer locations
within the XRT94L33, has now been selected.
5. Next, the µC/µP should indicate that this current bus cycle is a “Read” Operation by toggling the RdB_DS
(Read Strobe) input pin “low”. This action also enables the bi-directional data bus output drivers of the
XRT94L33. At this point, the “bi-directional” data bus output drivers will proceed to drive the contents of the
“latched addressed” register (or buffer location) onto the bi-directional data bus, D[7:0].
6.
Rdy_Dtck output pin “low”. The XRT94L33 does this in order to inform the µC/µP that the data (to be read
from the data bus) is “NOT READY” to be “latched” into the µC/µP.
7. After some settling time, the data on the “bi-directional” data bus will stabilize and can be read by the
µC/µP. The XRT94L33 will indicate that this data can be read by toggling the Rdy_Dtck (READY) signal
“high”.
8. After the µC/µP detects the Rdy_Dtck signal (from the XRT94L33 UNI), it can then terminate the Read
Cycle by toggling the RdB_DS (Read Strobe) input pin “high”.
Figure 4 presents a timing diagram which illustrates the behavior of the Microprocessor Interface signals,
during an “Intel-type” Programmed I/O Read Operation.
Immediately after the µC/µP toggles the “Read Strobe” signal “low”, the XRT94L33 will toggle the
P
ROGRAMMED
D
D
T
HE
ATA
ATA
I
NTEL
A
A
CCESS
CCESS USING
M
ODE
I/O A
M
ODES
R
CCESS IN THE
EAD
P
ROGRAMMED
C
YCLE
“I
NTEL
I/O
” M
129
ODE
XRT94L33
Rev.1.2.0.