XRT94L33IB-L Exar Corporation, XRT94L33IB-L Datasheet - Page 412

• Manufacturer Part Number: XRT94L33IB-L
• Description: IC MAPPER DS3/E3/STS-1 504TBGA
• Manufacturer: Exar Corporation

Specifications of XRT94L33IB-L

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 3.14 V ~ 3.47 V
• Package / Case: 504-LBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

XRT94L33
Rev.1.2.0.
Receive ATM Cell Processor Block – Receive ATM Control Register – Byte 1 (Address = 0xN702)
Setting this bit-field to “0” disables “Correction Mode” operation within the HEC Byte Verification Block.
Conversely, setting this bit-field to “1” enables “Correction Mode” operation within the HEC Byte Verification
Block.
The “Detection” State
Unless “Correction Mode” operation is disabled (per the procedure described above), the HEC Byte
Verification Block will transition into the “Detection” State (within the “HEC Byte Error Detection/Correction”
algorithm.
Whenever the “HEC Byte Verification” block is operating in the “Detection” State, then ALL errored cells (e.g.,
those incoming cells that contain single-bit errors and multi-bit errors) will be discarded, unless configured
otherwise by the user.
More specifically, whenever the HEC Byte Verification block detects ANY cells with header byte errors, then it
will do all of the following.
1.
Processor block will indicate that it is declaring the “Detection of Uncorrectable HEC Byte Error” Interrupt, by
doing the following.
2. It will increment the “Receive ATM Cell Processor Block – Receive ATM Cell with Uncorrectable HEC Byte
Error Count” Registers. This is a 32-bit RESET-upon-READ register that resides at Address Locations
0xN734 through 0xN737. The bit format of these registers is presented below.
Receive ATM Cell Processor Block – Receive ATM Cells with Uncorrectable HEC Byte Error Count
Register – Byte 3 (Address = 0xN734)
Receive ATM Cell Processor Block – Receive ATM Cells with Uncorrectable HEC Byte Error Count
Register – Byte 2 (Address = 0xN735)
B
R/O
B
RUR
B
RUR
a. Toggling the “INT*” output pin “low”.
b. Setting Bit 2 (Detection of Uncorrectable HEC Byte Error Interrupt Status), within the “Receive ATM
IT
It will generate the “Detection of Uncorrectable HEC Byte Error” Interrupt.
0
IT
IT
0
0
7
7
7
Cell Processor Block – Receive ATM Interrupt Status Register – Byte 0” to “1” as depicted below.
Unused
B
R/O
IT
0
B
RUR
B
RUR
6
IT
IT
0
0
6
6
Received Cells with Uncorrectable HEC Byte Error Count[31:24]
Received Cells with Uncorrectable HEC Byte Error Count[23:16]
B
R/O
IT
0
5
B
RUR
B
RUR
IT
IT
0
0
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
5
5
Extraction
Enable
B
GFC
R/W
IT
0
4
B
RUR
B
RUR
IT
IT
0
0
4
4
Correction
HEC Byte
Enable
B
R/W
412
IT
X
3
B
B
RUR
RUR
IT
IT
0
0
Uncorrectable
Error Discard
3
3
HEC Byte
B
R/W
IT
0
2
B
RUR
B
RUR
IT
IT
0
0
2
2
Polynomial
Addition
COSET
B
R/W
IT
1
1
The Receive ATM Cell
B
RUR
B
RUR
IT
IT
0
0
Regenerate
HEC Byte
1
1
xr
Enable
B
R/W
IT
0
0
B
RUR
B
RUR
IT
IT
0
0
0
0