XRT94L33IB-L Exar Corporation, XRT94L33IB-L Datasheet - Page 99

• Manufacturer Part Number: XRT94L33IB-L
• Description: IC MAPPER DS3/E3/STS-1 504TBGA
• Manufacturer: Exar Corporation

Specifications of XRT94L33IB-L

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 3.14 V ~ 3.47 V
• Package / Case: 504-LBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

xr
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
AD6
AF4
AE6
RxE1F1E2VAL
RxSDCCVAL
RXPOH
O
O
O
CMOS
CMOS
CMOS
Receive – Section DCC Output Port – DCC Value Indicator
Output pin:
This output pin, along with the “RxTOHClk” and the “RxSDCC”
output pins function as the “Receive Section DCC” output port of
the XRT94L33.
This output pin pulses “High” coincident to when the “Receive
Section DCC” output port outputs a DCC bit via the “RxSDCC”
output pin.
This output pin is updated upon the falling edge of “RxTOHClk”.
The Section DCC HDLC Controller circuitry that is interfaced to this
output pin, the “RxSDCC” and the “RxTOHClk” pins is suppose to
do the following.
It should continuously sample and monitor the state of this output
pin upon the rising edge of “RxTOHClk”.
Anytime the “Section DCC HDLC” circuitry samples this output pin
being “HIGH”, it should sample and latch the data on the
“RxSDCC” output pin (as a valid Section DCC bit) into the “Section
DCC HDLC” circuitry.
Receive – Order Wire Output Port – E1F1E2 Value Indicator
Output Pin:
This output pin, along with the “RxTOHClk”, “RxE1F1E2FP”,
“RxE1F1E2” and “RxTOHClk” output pins function as the “Receive
– Order Wire Output Port” of the XRT94L33.
This output pin pulses “high” coincident to when the “Receive –
Order Wire” output port outputs the contents of an E1, F1 or E2
byte, via the “RxE1F1E2” output pin.
This output pin is updated upon the falling edge of “RxTOHClk”.
The “Receive Order-Wire” circuitry, that is interfaced to this output
pin, the “RxE1F1E2” and the “RxTOHClk” pins is suppose to do the
following.
It should continuously sample and monitor the state of this output
pin upon the rising edge of “RxTOHClk”.
Anytime the “Receive Order-Wire” circuitry samples this output pin
being “high”, it should sample and latch the data on the
“RxE1F1E2” output pin (as a valid Order-wire bit) into the “Receive
Order-Wire” circuitry.
Receive AU-4/VC-4/STS-3c Mapper POH Processor Block –
Path Overhead Output Port – Output Pin:
This output pin, along with the “RxPOHClk”, “RxPOHFrame” and
“RxPOHValid” function as the “AU-4/VC-4 Mapper POH Processor
block – POH Output port.
These pins serially output the POH data that have been received
by the Receive AU-4/VC-4 Mapper POH Processor block (via the
“incoming” STS-3 data-stream). Each bit, within the POH bytes is
updated (via these output pins) upon the falling edge of
“RxPOHClk”. As a consequence, external circuitry receiving this
data, should sample this data upon the rising edge of “RxPOHClk”.
99
XRT94L33
Rev.1.2.0.