XRT94L33IB-L Exar Corporation, XRT94L33IB-L Datasheet - Page 407

• Manufacturer Part Number: XRT94L33IB-L
• Description: IC MAPPER DS3/E3/STS-1 504TBGA
• Manufacturer: Exar Corporation

Specifications of XRT94L33IB-L

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 3.14 V ~ 3.47 V
• Package / Case: 504-LBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
2.3.4.1.2
the HEC Byte Verification block will (as its name implies) perform “HEC Byte Verification” of incoming cells
data from the Receive STS-3c POH Processor block in order to protect against misrouted or mis-inserted
cells. In performing HEC Byte Verification the HEC Byte Verification block will take the first four byte of each
cells (e.g., the header bytes) and will independently compute its own value for the HEC byte. Afterwards, the
HEC Byte Verification block will compare its value of the HEC byte with the fifth octet that it has received from
the Receive STS-3c POH Processor block. If the two “HEC byte” values match then the “Receive ATM Cell
Processor” block will retain this cell for further processing. However, if the HEC Byte Verification block
detects errors in the header bytes of a cell, then the HEC Byte Verification block will call up and employ the
“HEC Byte Error Correction/Detection” Algorithm (see below).
The HEC Byte Verification block will compute its version of the HEC byte via the generating polynomial x
+ x + 1. The user should be aware that the HEC bytes of the incoming cell might have been modulo-2 added
with the Coset polynomial x
be configured to account for this by writing a “1” to Bit 1 (COSET Polynomial Addition) within the “Receive
ATM Cell Processor Block – Receive ATM Control Register – Byte 1.
Receive ATM Cell Processor Block – Receive ATM Control Register – Byte 1 (Address = 0xN702)
The “HEC Byte Error Correction/Detection” Algorithm
If the HEC Byte Verification block detects one or more errors in the header bytes of a given incoming ATM
cell, then the “HEC Byte Error Correction/Detection” algorithm will be employed. The “HEC Byte Error
Correction/Detection” Algorithm has two states: “Detection” Mode and “Correction” Mode.
Figure 99 presents a State Machine Diagram of the “HEC Byte Error Correction/Detection” Algorithm. Each
of these states is discussed below.
B
R/O
IT
0
7
HEC Byte VerificationOnce the HEC Byte Verification block is properly delineating cells, then
Unused
B
R/O
IT
0
6
6
+ x
B
R/O
4
IT
0
+ x
5
2
+ 1. If this is the case then the Receive ATM Cell Processor block must
Extraction
Enable
B
GFC
R/W
IT
0
4
407
Correction
HEC Byte
Enable
B
R/W
IT
1
3
Uncorrectable
Error Discard
HEC Byte
B
R/W
IT
0
2
Polynomial
Addition
COSET
B
R/W
IT
1
1
XRT94L33
Regenerate
HEC Byte
Enable
Rev.1.2.0.
B
R/W
IT
0
8
0
+ x
2