XRT94L33IB-L Exar Corporation, XRT94L33IB-L Datasheet - Page 303

• Manufacturer Part Number: XRT94L33IB-L
• Description: IC MAPPER DS3/E3/STS-1 504TBGA
• Manufacturer: Exar Corporation

Specifications of XRT94L33IB-L

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 3.14 V ~ 3.47 V
• Package / Case: 504-LBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
STEP 2 – Write the value “0” into Bit 7 (M0M1 Insert Method[0]) within the “Transmit STS-3 Transport
– SONET Transmit Control Register – Byte 0”; as depicted below.
Transmit STS-3 Transport – SONET Transmit Control Register – Byte 0 (Address = 0x1902)
Steps 1 and 2 configure the Transmit STS-3 TOH Processor block to automatically set bits 5 through 8 (of the
M0 Byte) within the “outbound” STS-3 data-stream, to the appropriate REI-L value based upon receive
conditions as detected by the corresponding “Receive STS-3 TOH Processor” block.
STEP 3 – Indicate whether or not the REI-L value (transmitted to the remote LTE) reflects the number
of bits (within the B2 byte) that are in error, or the number of erred STS-3 frames that have been
detected by the corresponding Receive STS-3 TOH Processor block.
The XRT94L33 permits the user to (1) flag B2 byte errors, and (2) to transmit the resulting REI-L values (back
to the remote LTE) by the following means.
• By flagging and reporting the number of bits (within the B2 byte(s)) that have been determined to be in
error, within a given STS-3 frame.
• By flagging and reporting whether or not the corresponding Receive STS-3 TOH Processor block is
currently receiving an erred STS-3 frame.
The user can choose between these two options by writing the appropriate value into Bit 1 (B2 Error Type)
within the “Receive STS-3 Transport – Control Register – Byte 0”, as depicted below.
Receive STS-3 Transport Control Register – Byte 0 (Address = 0x1103)
Setting this bit-field to “0” configures the “Transmit STS-3 TOH Processor” block to set the REI-L bit-fields
(within the M0 byte) of the “outbound” STS-3 frame to a value that reflects the number of bits (within the B2
byte) that were determined to be in error (within the most recently received STS-3 frame) by the
corresponding Receive STS-3 TOH Processor block. In this case, the REI-L bit-fields can range in value from
“0” (for no B2 byte errors) to “8” (for all B2 bits being in error).
Setting this bit-field to “1” configures the “Transmit STS-3 TOH Processor” block to set the REI-L bit-fields
(within the M0 byte) of the “outbound” STS-3 frame; to a value that indicates whether or not at least one B2 bit
error was detected within the most recently received STS-3 frame; by the corresponding Receive STS-3 TOH
Processor block. In this mode, the Transmit STS-3 TOH Processor block will set the “REI-L” bit-fields (within
the “outbound” STS-3 frame) to “0” if the corresponding Receive STS-3 TOH Processor block is not detecting
any B2 byte errors, in its incoming STS-3 data-stream.
Conversely, the Transmit STS-3 TOH Processor block will set the “REI-L” bit-fields (within the “outbound”
STS-3 frame) to “1” if the corresponding Receive STS-3 TOH Processor block receives an STS-3 frame that
contains a B2 byte error.
M0M1 Insert
Method[0]
Unused
B
B
R/W
R/O
IT
IT
0
0
7
7
SF Detect
Enable
Unused
B
R/W
B
R/O
IT
0
IT
0
6
6
RDI-L Force
SD Detect
Enable
B
R/W
B
R/W
IT
0
IT
0
5
5
Descramble
AIS-L Force
Disable
B
R/W
B
R/W
IT
0
IT
0
4
4
303
SDH/SONET*
LOS Force
B
R/W
B
R/W
IT
0
IT
0
3
3
REI-L Error
Scramble
Enable
B
R/W
B
Type
R/W
IT
0
IT
0
2
2
B2 Error
B2 Error
Insert
B
R/W
B
Type
R/W
IT
0
IT
X
1
1
XRT94L33
A1A2 Error
B1 Error
Rev.1.2.0.
Insert
B
B
Type
R/W
R/W
IT
0
IT
0
0
0