XRT94L33IB-L Exar Corporation, XRT94L33IB-L Datasheet - Page 368

• Manufacturer Part Number: XRT94L33IB-L
• Description: IC MAPPER DS3/E3/STS-1 504TBGA
• Manufacturer: Exar Corporation

Specifications of XRT94L33IB-L

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 3.14 V ~ 3.47 V
• Package / Case: 504-LBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

XRT94L33
Rev.1.2.0.
Note:
Receive STS-3 Transport Interrupt Status Register – Byte 0 (Address = 0x110B)
•
Receive STS-3 Transport Status Register – Byte 0 (Address = 0x1107)
2.3.1.13.3
The XRT94L33 permits the user to specify the following two parameters to define the SD Defect Clearance
criteria.
•
•
Once the user defines these parameters, then the Receive STS-3 TOH Processor block will begin to count
the cumulative number of B2 byte errors that it detects within a “sliding window” of time. The length of this
“sliding window of time” is dictated by the user-defined “SD Defect Clear Monitor” time period.
If the Receive STS-3 TOH Processor block is currently declaring the SD Defect condition, and if continues to
detects more than the “SD Defect Clear B2 error threshold” number of B2 errors; within the “SD Defect Clear
Monitor” of time, then it will NOT clear the SD defect condition. Conversely, if the Receive STS-3 TOH
Processor block detects less than the “SD Defect Clear B2 byte error threshold” number of B2 byte errors,
within the “SD Defect Clear Monitor” period of time, then it will clear the SD defect condition.
Specifying the “B2 Byte Error Threshold” for Clearing the SD Defect Condition
The user can specify the “SD Defect Clear B2 Byte Error Threshold” by writing the appropriate value into the
“Receive STS-3 Transport – Receive SD Clear Threshold – Byte 1 and Byte 0” registers, as depicted below.
Change of
SF Defect
Condition
Declared
Interrupt
Status
Defect
RDI-L
B
RUR
B
It will set Bit 3 (SD Defect Declared), within the “Receive STS-3 Transport Status Register – Byte 0” to
“1”, as depicted below.
R/O
The maximum number of B2 errors (e.g., a B2 byte error-threshold) accumulated over a given “SD Defect
Clear Monitor” time period.
The length of this “SD Defect Clear Monitor” time period.
IT
IT
0
0
7
7
The Receive STS-3 TOH Processor block will indicate that it is generating this interrupt by toggling the “INT*”
output pin “low” and by setting the “Change of SD Defect Condition Interrupt Status” bit to “1”, as depicted
below.
The SD (Signal Degrade) Defect Clearance Criteria
Change of
SD Defect
Condition
Unstable
Declared
Interrupt
S1 Byte
Defect
Status
B
RUR
B
R/O
IT
IT
1
0
6
6
Detection of
K1, K2 Byte
REI-L Error
Declared
Unstable
Interrupt
Status
Defect
B
RUR
B
R/O
IT
IT
0
0
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
5
5
Detection of
SF Defect
Declared
Interrupt
B2 Byte
Status
B
Error
B
RUR
R/O
IT
IT
0
0
4
4
368
Detection of
SD Defect
Declared
Interrupt
B1 Byte
Status
B
Error
RUR
B
R/O
IT
IT
0
1
3
3
LOF Defect
LOF Defect
Change of
Condition
Declared
Interrupt
Status
B
B
RUR
R/O
IT
IT
0
0
2
2
SEF Defect
SEF Defect
Change of
Condition
Declared
Interrupt
Status
B
RUR
B
R/O
IT
IT
0
0
1
1
xr
LOS Defect
LOS Defect
Change of
Condition
Declared
Interrupt
Status
B
RUR
B
R/O
IT
IT
0
0
0
0