XRT94L33IB-L Exar Corporation, XRT94L33IB-L Datasheet - Page 345

• Manufacturer Part Number: XRT94L33IB-L
• Description: IC MAPPER DS3/E3/STS-1 504TBGA
• Manufacturer: Exar Corporation

Specifications of XRT94L33IB-L

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 3.14 V ~ 3.47 V
• Package / Case: 504-LBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

xr
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
Receive STS-3 Transport Interrupt Status Register – Byte 0 (Address = 0x110B)
2.3.1.3.6.2
Once the Receive STS-3 TOH Processor block has declared the LOF defect condition, then it will clear the
LOF only after both of the following conditions have been met.
The user can specify the “LOF Clearance Criteria” by writing the appropriate value (in terms of numbers of
consecutive STS-3 frames with un-erred A1 and A2 bytes) into Bits 3 through 0 (In-Sync Threshold) within the
“Receive STS-3 Transport – In Sync Threshold” Register, as depicted below.
Receive STS-3 Transport – In-Sync Threshold Value (Address =0x112B)
Once the Receive STS-3 TOH Processor block has cleared the SEF defect, then it will proceed to check for
the occurrence of “In-Sync Threshold[3:0]” number of incoming STS-3 frames that contain un-erred A1 and
A2 bytes. Once all of this has occurred then the Receive STS-3 TOH Processor block will clear the LOF
defect condition.
Once the Receive STS-3 TOH Processor block clears the LOF condition, then it will alert the Microprocessor
of this fact by doing the following.
Change of
SF Defect
Condition
Declared
Interrupt
Defect
Status
B
B
RUR
R/O
10. It will generate the “Change of LOF Defect Condition” Interrupt. The Receive STS-3 TOH Processor
11. That the Receive STS-3 TOH Processor block has cleared the SEF defect.
12. If it detects a “user-specified” number of consecutive STS-3 frames with un-erred framing alignment
R/O
13. It will indicate that it is clearing the LOF defect condition by setting Bit 2 (LOF Defect Declared) within
IT
IT
0
0
0
7
7
block will indicate that it is declaring the “Change of LOF Defect Condition” interrupt by doing the
following.
a. Toggling the “INT*” output pin “low”.
b. Setting Bit 2 (Change of LOF Defect Condition Interrupt Status) within the Receive STS-3
(e.g., A1 and A2) bytes.
the Receive STS-3 Transport Status Register – Byte 0” to “0” as depicted below.
Transport Interrupt Status Register – Byte 0 to “1” as depicted below.
Change of
SD Defect
Condition
Unstable
Declared
Interrupt
How the Receive STS-3 TOH Processor Block clears the LOF Defect Condition
Unused
Defect
Status
B
RUR
B
R/O
R/O
IT
IT
0
0
0
6
6
Detection of
REI-L Error
Declared
Unstable
Interrupt
Defect
Status
B
RUR
B
R/O
R/O
IT
IT
0
0
0
5
5
Detection of
Declared
Interrupt
B2 Byte
Status
B
Error
RUR
B
R/W
R/O
IT
IT
0
0
0
FRPATOUT[1:0]
4
4
345
Detection of
Declared
Interrupt
B1 Byte
Status
Error
B
RUR
B
R/W
R/O
IT
IT
0
0
0
3
3
LOF Defect
Change of
Condition
Declared
Interrupt
Status
B
RUR
B
R/W
R/O
IT
IT
1
1
0
FRPATIN[1:0]
2
2
SEF Defect
Change of
Condition
Declared
Interrupt
Status
B
RUR
B
R/W
R/O
IT
IT
0
0
0
1
1
XRT94L33
LOS Defect
Change of
Condition
Declared
Interrupt
Unused
Status
Rev.1.2.0.
B
RUR
B
R/O
R/O
IT
IT
0
0
0
0
0