XRT94L33IB-L Exar Corporation, XRT94L33IB-L Datasheet - Page 448

• Manufacturer Part Number: XRT94L33IB-L
• Description: IC MAPPER DS3/E3/STS-1 504TBGA
• Manufacturer: Exar Corporation

Specifications of XRT94L33IB-L

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 3.14 V ~ 3.47 V
• Package / Case: 504-LBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

XRT94L33
Rev.1.2.0.
reception of the cell currently being read out, and to proceed with reading out the next ATM cell from the
Receive UTOPIA Interface only if RxUClav is at a logic “high”.
Figure 113 presents a timing diagram of that illustrates the behavior of various Receive UTOPIA Interface
block signals, when the Receive UTOPIA Interface block is operating the “Cell-Level” Handshaking Mode.
Figure 113 Timing Diagram of various Receive UTOPIA Interface block signals, when the Receive
UTOPIA Interface block is operating in the “Cell Level Handshaking” Mode
Notes:
In Figure 113 the ATM Layer processor is just finishing up its reading of an ATM cell. Prior to clock edge #2,
the RxFIFO does not contain enough ATM cell data to make up at least one cell. Hence, the Receive
UTOPIA Interface block negates the RxUClav signal. The ATM Layer processor detects that the RxClav
signal has toggled “low”; at clock edge #2. Hence, the ATM Layer processor will finish reading in the current
ATM cell; from the Receive UTOPIA Interface block of the XRT94L33 (e.g., words W25 and W26).
Afterwards, the ATM Layer processor will negate the RxUEnB* signal and will cease to read in anymore ATM
cell data from the Receive UTOPIA Interface block; until RxUClav toggles “high” again.
The RxFIFO accumulates enough cell data to make up a complete ATM cell shortly before clock edge #5. At
this point the Receive UTOPIA Interface block reflects this fact by asserting the RxUClav signal. The ATM
Layer processor detects that the RxUClav signal has toggled “high” at clock edge #5. Consequently, the ATM
Layer processor then asserts the RxUEnB* signal (e.g., toggles it “low”) after clock edge #5. The Receive
UTOPIA Interface block detects the fact that the RxUEnB* input pin has been asserted at clock edge #6. The
Receive UTOPIA Interface block then responds to this signaling by placing the first word of the next cell on
the Receive UTOPIA Data bus. Afterwards, the ATM Layer processor continues to read in the remaining
words of this cell.
2.3.5.1.2.3
The XRT94L33 can be configured to support either Single-PHY or Multi-PHY operation. Each of these
operating modes is discussed below.
2.3.5.1.2.4
The XRT94L33 permits the user to configure it to operate in either the “Single-PHY” or “Multi-PHY” Mode.
The user can configure the chip to operate in the “Single-PHY” Mode by setting Bit 6 (Multi-PHY Mode) to “0”;
as illustrated below.
Receive UTOPIA/POS-PHY Control Register – Byte 0 (Address = 0x0503)
The Receive UTOPIA Data bus is configured to be 16 bits wide. Hence, the data, which the Receive UTOPIA places on
The Receive UTOPIA Interface block is configured to handle 54 bytes/cell. Hence, Figure 86 illustrates the ATM Layer
RxData[15:0]
the Receive UTOPIA Data bus, is expressed in terms of 16 bit words: W0 - W26.
processor reading in 27 words (W0 through W26) for each ATM cell.
RxEnB*
RxClav
RxSoC
RxClk
regarding Figure 113:
W24
1
UTOPIA Modes of Operation (Single PHY and Multi-PHY operation)
Single PHY Operation
W25
2
W26
3
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
4
5
6
448
W0
7
W1
8
W2
9
31
W25
32
W26
xr
34