XRT94L33IB-L Exar Corporation, XRT94L33IB-L Datasheet - Page 9

• Manufacturer Part Number: XRT94L33IB-L
• Description: IC MAPPER DS3/E3/STS-1 504TBGA
• Manufacturer: Exar Corporation

Specifications of XRT94L33IB-L

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 3.14 V ~ 3.47 V
• Package / Case: 504-LBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

xr
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
AG22
AF21
AF20
AB24
AE18
P
T3
IN
#
DIRECT_ADD_SEL
S
RXLDAT_P
PBLAST_L
PDBEN_L
IGNAL
RESET_L
PINT_L
N
AME
I/O
O
I
I
I
I
I
SONET/SDH S
LVPECL
S
CMOS
T
TTL
TTL
TTL
TTL
IGNAL
YPE
ERIAL
Bi-directional Data Bus Enable Input pin:
This input pin permits the user to either enable or tri-state the Bi-
Directional Data Bus pins (D[7:0]), as described below.
Setting this input pin “low” enables the Bi-directional Data bus.
Setting this input “high” tri-states the Bi-directional Data Bus.
Last Burst Transfer Indicator input pin:
If the Microprocessor Interface is operating in the Intel-I960
Mode, then this input pin is used to indicate (to the
Microprocessor Interface block) that the current data transfer is
the last data transfer within the current burst operation.
The Microprocessor should assert this input pin (by toggling it
“Low”) in order to denote that the current READ or WRITE
operation (within a BURST operation) is the last operation of this
BURST operation.
Note:
Interrupt Request Output:
This open-drain, active-low output signal will be asserted when
the Mapper/Framer device is requesting interrupt service from
the Microprocessor.
connected to the “Interrupt Request” input of the Microprocessor.
Reset Input:
When this “active-low” signal is asserted, the XRT94L33 will be
asynchronously reset. When this occurs, all outputs will be “tri-
stated” and all on-chip registers will be reset to their “default”
values.
Address Location Select input pin:
This input pin must be pulled “HIGH” in order to permit normal
operation of the Microprocessor Interface.
Receive STS-3/STM-1 Data – Positive Polarity PECL Input:
This input pin, along with RXLDAT_N functions as the
Recovered Data Input, from the Optical Transceiver or as the
Receive Data Input from the system back-plane
Note:
9
L
INE
The user should connect this input pin to GND
whenever the Microprocessor Interface has been
configured to operate in the Intel-Async, Motorola 68K
and IBM PowerPC 403 modes.
this input pin, along with “RXLDAT_N” functions as the
“Primary” STS-3/STM-1 Receive Data Input Port.
I
For APS (Automatic Protection Switching) purposes,
NTERFACE
P
INS
This output pin should typically be
D
ESCRIPTION
XRT94L33
Rev.1.2.0.