XRT94L33IB-L Exar Corporation, XRT94L33IB-L Datasheet - Page 458

• Manufacturer Part Number: XRT94L33IB-L
• Description: IC MAPPER DS3/E3/STS-1 504TBGA
• Manufacturer: Exar Corporation

Specifications of XRT94L33IB-L

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 3.14 V ~ 3.47 V
• Package / Case: 504-LBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

XRT94L33
Rev.1.2.0.
2.3.5.1.2.8
Figure 117depicts a “Multi-PHY” system consisting of a single ATM Layer processor and two (2) UNI devices,
which are designated as “UNI #1” and “UNI #2”. In this figure, both of the UNIs are connected to the ATM
Layer processor via a common “Transmit UTOPIA” Data Bus, a common “Receive UTOPIA” Data Bus, a
common “TxUClav” line, a common “RxUClav” line, as well as common TxUEnB*, RxUEnB*, TxUSoC and
RxUSoC lines. The ATM Layer processor will also be addressing both the Transmit and Receive UTOPIA
Interface blocks via a common “UTOPIA” address bus (Ut_Addr[4:0]) Therefore, the Transmit and Receive
UTOPIA Interface Blocks, within a given UNI might have different addresses; as depicted in Figure 117.
The UTOPIA Address values, that have been assigned to each of the Transmit and Receive UTOPIA
Interface blocks, within Figure 26, are listed below in Table 24.
Table 24 UTOPIA Address Values of the UTOPIA Interface blocks illustrated in Figure 117.
Recall, that the Receive UTOPIA Interface blocks were assigned these addresses by writing these values into
registers that are similar to the “Receive UTOPIA Port Number (Address = 0x0517) and the Receive UTOPIA
Address Register” (Address = 0x0513) within these UNI devices. The discussion of the Transmit UTOPIA
Interface blocks, within UNIs #1 and #2 is presented in Section _.
Polling Operation
Consider that the ATM Layer processor is currently reading a continuous stream of ATM cell data from UNI
#1. While reading this ATM cell data from UNI #1, the ATM Layer processor can also “poll” UNI #2 for
“availability” (e.g., tries to determine if UNI # 2 contains any ATM cells, within its RxFIFO, that needs to be
read out via its Receive UTOPIA Interface block).
The ATM Layer processor’s role in the “polling” operation
The ATM Layer processor accomplishes this “polling” operation by executing the following steps.
1. Assert the RxUEnB* input pin (if it is not asserted already).
The UNI device (being “polled”) will know that this is only a “polling” operation, if the RxUEnB* input pin is
asserted, prior to detecting its UTOPIA Address on the “UTOPIA Address” bus (RxUAddr[4:0]).
2. The ATM Layer processor places the address of the Receive UTOPIA Interface Block of UNI #2 onto
the UTOPIA Address Bus, Ut_Addr[4:0],
3. The ATM Layer processor will then check the value of its “RxUClav_in” input pin (see Figure 117).
The ATM Layer Processor is suppose to check the state of the “RxUClav” signal, one “RxUClk” period after
placing the UTOPIA Address (corresponding to a particular UNI device) on the “RxUAddr[4:0]” input pins. If
“RxUClav” is sampled “high” then this means that this particular UNI device contains at least one ATM cell of
data (within its RxFIFO) that needs to be read out by the ATM Layer Processor. Conversely, if RxUClav is
sampled “low” then this means that this particular UNI device does not contain at least one ATM cell of data
within its RxFIFO, that needs to be read out via the ATM Layer Processor.
The UNI devices role in the “polling” operation
UNI #2 will sample the signal levels placed on its Rx UTOPIA Address input pins (RxUAddr[4:0]) on the rising
edge of its “Receive UTOPIA Interface block” clock input signal, RxUClk. Afterwards, UNI #2 will compare the
Transmit UTOPIA Interface block - UNI #1
Transmit UTOPIA Interface block - UNI #2
Receive UTOPIA Interface block - UNI #1
Receive UTOPIA Interface block - UNI #2
ATM Layer Processor “polling” in a Conceptual Multi-PHY System
B
LOCK
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
458
UTOPIA A
0x00
0x01
0x02
0x03
DDRESS
V
ALUE
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