XRT94L33IB-L Exar Corporation, XRT94L33IB-L Datasheet - Page 123

• Manufacturer Part Number: XRT94L33IB-L
• Description: IC MAPPER DS3/E3/STS-1 504TBGA
• Manufacturer: Exar Corporation

Specifications of XRT94L33IB-L

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 3.14 V ~ 3.47 V
• Package / Case: 504-LBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
1.2.10
The purpose of the “Transmit STS-3 TOH Processor” block is to perform the following functions.
• To generate and insert the TOH (for the “outbound” STS-3 signal) prior to transmission to the remote LTE.
• To automatically transmit the RDI-L indicator (to the remote LTE) upon detection of the following defect
conditions by the corresponding Receive STS-3 TOH Processor block.
• To transmit the RDI-L indicator upon software control.
• To automatically transmit the REI-L indicator (to the remote LTE) upon detection of B2 byte errors by the
Receive STS-3 TOH Processor block.
• To transmit the REI-L indicator upon software control.
• To transmit the AIS-L indicator (to the remote LTE) upon software command.
1.2.11
The purpose of the Transmit STS-3 PECL Interface block is to accept STS-3 data from the Transmit STS-3
TOH Processor block and to perform the following functions on this signal.
• Converting this “outbound” CMOS-level signal into the LVPECL format.
• To output this STS-3 PECL signal to either the System Back-plane (for transmission to a “Concentrator”
Board) or to an Optical Transceiver, for transmission to remote terminal equipment.
1.3
The purpose of the Microprocessor Interface block is to support the following operations between the user’s
Microprocessor/Microcontroller and the XRT94L33.
• Writing/Loading configuration information into the “on-chip” Command Registers; within the XRT94L33.
• Reading out the state of various bit-fields, reflecting Alarm conditions.
• Writing in the contents of “outbound” J0 (Section Trace) Messages into the “Transmit J0 (Section Trace)
Message” buffer.
• Reading out the contents of “inbound” J0 Messages from the “Receive J0 (Section Trace) Message” buffer.
•
Message” buffer.
• Reading out the contents of “inbound” J1 Messages from the “Receive J1 (Path Trace) Message” buffer.
• Writing the contents of “outbound” ATM (OAM) cells into the Transmit Cell Insertion Memory within the
Transmit ATM Cell Processor block
• Reading the contents of certain “outbound” ATM cells from the Transmit Cell Extraction Memory within the
Transmit ATM Cell Processor block.
• Reading the contents of “inbound” ATM (OAM) cells from the Receive Cell Extraction Memory within the
Receive ATM Cell Processor block.
Writing in the contents of “outbound” J1 (Path Trace) Messages into the “Transmit J1 (Path Trace)
a. LOS
b. LOF
c. AIS-L
d. SD
e. SF
THE MICROPROCESSOR INTERFACE
T
T
HE
HE
T
T
RANSMIT
RANSMIT
STS-3 TOH P
STS-3 PECL I
ROCESSOR
NTERFACE
B
B
LOCK
LOCK
123
XRT94L33
Rev.1.2.0.