XRT94L33IB-L Exar Corporation, XRT94L33IB-L Datasheet - Page 208

• Manufacturer Part Number: XRT94L33IB-L
• Description: IC MAPPER DS3/E3/STS-1 504TBGA
• Manufacturer: Exar Corporation

Specifications of XRT94L33IB-L

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 3.14 V ~ 3.47 V
• Package / Case: 504-LBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

XRT94L33
Rev.1.2.0.
Enabling the Transmit Cell Extraction Interrupt
The user can enable the “Transmit Cell Extraction” Interrupt by executing the following steps.
STEP 1 – Write the value “1” into Bit 3 (Transmit ATM Cell Processor Block Interrupt Enable), within
the “Operation Block Interrupt Enable Register – Byte 0”, as depicted below.
Operation Block Interrupt Enable Register – Byte 0 (Address = 0x0017)
Note:
STEP 2 – Set Bit 5 (Cell Extraction Interrupt Enable), within the “Transmit ATM Cell Processor –
Interrupt Enable Register” to “1” as depicted below.
Transmit ATM Cell Processor – Interrupt Enable Register (Address = 0xNF0F)
This step enables the “Transmit Cell Extraction” Interrupt, at the “Source-Level”. Once the user executes this
write operation, then the Transmit ATM Cell Processor block will generate an interrupt to the Microprocessor
anytime that the User Cell Filter copies a cell, and routes the “replicate” cell to the “Transmit Cell Extraction
Buffer”.
Servicing the Transmit Cell Extraction Interrupt
Once the XRT94L33 generates an interrupt, then the user must develop the Interrupt Service routine such
that it executes the following steps.
Processor
ATM Cell
Interrupt
Receive
Enable
Block
B
R/W
IT
0
7
B
This step enables the “Transmit ATM Cell Processor” block for Interrupt Generation, at the “Block Level”.
R/O
IT
0
7
Unused
Interrupt
Receive
Enable
STS-3
Block
B
TOH
R/W
B
R/O
IT
0
IT
0
6
6
Extraction
POH Block
Interrupt
Enable
SONET/
Interrupt
Receive
Enable
B
R/W
Cell
VC-3
B
R/W
IT
1
IT
0
5
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
5
Insertion
Interrupt
Enable
Processor
B
R/W
Interrupt
Receive
Cell
Enable
IT
Block
0
B
PPP
R/W
4
IT
0
4
208
Extraction
Overflow
Interrupt
Memory
Enable
B
R/W
Processor
Cell
ATM Cell
Transmit
Interrupt
IT
0
Enable
Block
B
R/W
3
IT
1
3
Insertion
Overflow
Interrupt
Memory
Enable
B
R/W
Cell
IT
0
2
B
R/O
IT
0
2
Unused
Byte Error
Detection
Interrupt
of HEC
Enable
B
R/W
IT
0
1
B
R/O
IT
0
1
xr
Detection
Interrupt
of Parity
Enable
B
Error
R/W
IT
0
Processor
0
Transmit
Interrupt
Enable
Block
B
PPP
R/W
IT
0
0