XRT94L33IB-L Exar Corporation, XRT94L33IB-L Datasheet - Page 213

• Manufacturer Part Number: XRT94L33IB-L
• Description: IC MAPPER DS3/E3/STS-1 504TBGA
• Manufacturer: Exar Corporation

Specifications of XRT94L33IB-L

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 3.14 V ~ 3.47 V
• Package / Case: 504-LBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

xr
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
STEP 3 – After the Microprocessor has determined which of the four Transmit ATM Cell Processor
blocks is the “Interrupting” block within the XRT94L33, then it should read out the contents of the
corresponding “Transmit ATM Cell Processor – Interrupt Status Register”.
This will permit the Microprocessor to identify the exact cause of the interrupt request, from the Transmit ATM
Cell Processor block.
presented below.
Transmit ATM Cell Processor – Interrupt Status Register (Address = 0xNF0B)
If the cause of this interrupt is the “Transmit Cell Insertion” Interrupt, then Bit 4 (Cell Insertion Interrupt Status)
within the “Transmit ATM Cell Processor – Interrupt Status Register” will be set to “1” as depicted above.
Recommended Subsequent Action
Once the Microprocessor Interface has identified this particular interrupt as being the “Transmit Cell Insertion”
Interrupt, then this means that some space within the Transmit Cell Insertion Buffer has been “freed-up”. As a
consequence, the user can respond to this interrupt by writing in another ATM cell into the Transmit Cell
Insertion Buffer. The procedure for writing the contents of an ATM cell into the “Transmit Cell Insertion” Buffer
is presented in Section 4.2.2.3.
The Transmit Cell Extraction Memory Overflow Interrupt
The Transmit ATM Cell Processor block will generate the “Transmit Cell Extraction Memory Overflow”
Interrupt anytime the Transmit Cell Extraction buffer is currently full, and the Transmit Cell Extraction
Processor reads in another “copied” ATM cell into the “Transmit Cell Extraction” buffer. In this case, some of
the data residing within the “Transmit Cell Extraction” buffer will be overwritten and will be lost.
Note:
Enabling the “Transmit Cell Extraction Memory Overflow” Interrupt
The user can enable the “Transmit Cell Extraction Memory Overflow” Interrupt by executing the following
steps.
B
R/O
IT
0
7
Unused
If the “Transmit ATM Cell Processor” block generates the “Transmit Cell Extraction” Memory Overflow Interrupt
this is typically the result of the Microprocessor not reading out the contents of the Transmit Cell Extraction
Memory quickly or often enough before another ATM cell is “copied” by the Transmit User Cell” Filter.
Additionally, this particular interrupt should serve as a warning that the “Transmit Cell Extraction” Buffer likely
contains some erred data.
B
R/O
IT
0
6
The bit-format of “Transmit ATM Cell Processor – Interrupt Status” Register is
Extraction
Interrupt
Status
B
RUR
Cell
IT
0
5
Insertion
Interrupt
Status
B
RUR
Cell
IT
1
4
213
Extraction
Overflow
Interrupt
Memory
Status
B
RUR
Cell
IT
0
3
Cell Insertion
Overflow
Interrupt
Memory
Status
B
RUR
IT
0
2
Detection of
HEC Byte
Interrupt
Status
B
Error
RUR
IT
0
1
XRT94L33
Detection of
Parity Error
Interrupt
Status
Rev.1.2.0.
B
RUR
IT
0
0