XRT94L33IB-L Exar Corporation, XRT94L33IB-L Datasheet - Page 205

• Manufacturer Part Number: XRT94L33IB-L
• Description: IC MAPPER DS3/E3/STS-1 504TBGA
• Manufacturer: Exar Corporation

Specifications of XRT94L33IB-L

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 3.14 V ~ 3.47 V
• Package / Case: 504-LBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
The user can implement this configuration option by writing a “1” into Bit 1 (Coset Addition) within the
“Transmit ATM Control – Byte 1” Register, as depicted below.
Transmit ATM Control – Byte 1 (Address = 0xNF02)
Note:
Inverting the HEC Byte
The “HEC Byte Calculation & Insertion” block permits the user to configure it to invert the value of each of the
eight bits within the HEC byte of each outbound ATM cell. The user can implement this configuration option
by executing the following steps.
STEP 1 – Configure the “HEC Byte Calculation & Insertion” block to compute and insert the HEC byte
into the fifth octet position, within each “outbound” ATM cell.
This is accomplished by setting Bit 0 (Re-Calculate HEC Byte Enable), within the “Transmit ATM Control –
Byte 1” register to “1”, as depicted below.
Transmit ATM Control – Byte 1 (Address = 0xNF02)
STEP 2 – Configure the “HEC Calculation & Insertion” Block to now invert the contents of the HEC
byte that it is computing.
This is accomplished by setting Bit 7 (HEC Byte Invert), within the “Transmit ATM Control – Byte 0” Register
to “1” as depicted below.
Transmit ATM Control – Byte 0 (Address = 0xNF03)
HEC Byte
Test Cell
Test Cell
Enable
Enable
Mode
Mode
Invert
B
B
B
R/W
R/W
R/W
IT
IT
IT
0
0
1
7
7
7
In order to configure the “HEC Byte Calculation & Insertion” block to add the Coset polynomial to the HEC byte, it
is imperative that the user also set Bit 0 (Re-Calculate HEC Byte Enable), within the same register; to “1” as
depicted above.
Generator –
Generator –
HEC Byte
One Shot
One Shot
Test Cell
Test Cell
Enable
Check
B
R/W
B
B
R/W
R/W
IT
0
IT
IT
0
0
6
6
6
Parity Check
Enable
B
R/W
B
B
R/W
R/W
IT
0
IT
IT
0
0
5
5
5
Discard Cell
upon Parity
Error
B
R/W
B
B
R/W
R/W
IT
X
GFC_Enable[3:0]
GFC_Enable[3:0]
IT
IT
0
0
4
4
4
205
Odd Parity
B
R/W
B
B
R/W
R/W
IT
X
IT
IT
0
0
3
3
3
B
R/O
B
B
R/W
R/W
IT
0
IT
IT
0
0
2
2
2
Unused
Addition
Addition
Coset
Coset
B
B
B
R/O
R/W
R/W
IT
0
IT
IT
X
1
1
1
1
XRT94L33
Cell Payload
Scramble
HEC Byte
HEC Byte
Calculate
Calculate
Enable
Enable
Enable
Rev.1.2.0.
B
B
B
R/W
R/W
R/W
Re-
Re-
IT
X
IT
IT
1
1
0
0
0