XRT94L33IB-L Exar Corporation, XRT94L33IB-L Datasheet - Page 203

• Manufacturer Part Number: XRT94L33IB-L
• Description: IC MAPPER DS3/E3/STS-1 504TBGA
• Manufacturer: Exar Corporation

Specifications of XRT94L33IB-L

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 3.14 V ~ 3.47 V
• Package / Case: 504-LBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

xr
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
•
Transmit ATM Cell – HEC Byte Error Count Register – Byte 3 (Address = 0xNF30)
Transmit ATM Cell – HEC Byte Error Count Register – Byte 2 (Address = 0xNF31)
Transmit ATM Cell – HEC Byte Error Count Register – Byte 1 (Address = 0xNF32)
Transmit ATM Cell – HEC Byte Error Count Register – Byte 0 (Address = 0xNF33)
In general, if the HEC Byte Calculation & Insertion block detects ATM cells that contains “Single-Bit” or “Multi-
Bit” errors (within the Header bytes), then it will NOT correct these Header byte errors. Further, the Transmit
ATM Cell Processor block will automatically discard these erred cells unless it has been configured to
recalculate and insert a new HEC byte into the 5
Section 4.2.2.7.2).
Note:
If the user does not wish to configure the “HEC Byte Calculation & Insertion” block to check for HEC byte
errors in the incoming ATM cell data-stream, then they should set Bit 6 (HEC Byte Check Enable), within the
Transmit ATM Control – Byte 0 register to “0” as indicated below.
B
B
B
B
RUR
RUR
RUR
RUR
Finally, the Transmit ATM Cell Processor block will increment the “Transmit ATM Cell – HEC Byte Error
Count” register. The “Transmit ATM Cell” HEC Byte Error Count Register is a 32-bit “RESET-upon-
READ” register. The bit-format for this register is presented below.
0
IT
IT
IT
IT
0
0
0
0
7
7
7
7
The Transmit ATM Cell – HEC Byte Error Count Register will be incremented by the value “1” each time the
Transmit ATM Cell Processor detects a HEC byte error in the incoming ATM cell stream. This 32-bit register
will continue to be incremented until it reaches the value “0xFFFFFFFF”. At this point, this RESET-upon-READ
register will saturate and will not increment any further, until the Microprocessor reads out the contents of these
registers.
0
B
RUR
B
RUR
B
RUR
B
RUR
IT
IT
IT
IT
0
0
0
0
6
6
6
6
0
B
RUR
B
RUR
B
RUR
B
RUR
IT
IT
IT
IT
0
0
0
0
5
5
5
5
Transmit_HEC_Byte_Error_Count[31:24]
Transmit_HEC_Byte_Error_Count[23:16]
Transmit_HEC_Byte_Error_Count[15:8]
Transmit_HEC_Byte_Error_Count[7:0]
0
B
RUR
B
RUR
B
RUR
B
RUR
IT
IT
IT
IT
0
0
0
0
4
4
4
4
th
octet position of each ATM cell (as discussed below in
203
0
B
RUR
B
RUR
B
RUR
B
RUR
IT
IT
IT
IT
0
0
0
0
3
3
3
3
B
RUR
B
RUR
B
RUR
B
RUR
0
IT
IT
IT
IT
0
0
0
0
2
2
2
2
B
RUR
B
RUR
B
RUR
B
RUR
1
IT
IT
IT
IT
0
0
0
0
1
1
1
1
XRT94L33
Rev.1.2.0.
B
RUR
B
RUR
B
RUR
B
RUR
0
IT
IT
IT
IT
0
0
0
0
0
0
0
0