XRT94L33IB-L Exar Corporation, XRT94L33IB-L Datasheet - Page 436
XRT94L33IB-L
Manufacturer Part Number
XRT94L33IB-L
Description
IC MAPPER DS3/E3/STS-1 504TBGA
Manufacturer
Exar Corporation
Specifications of XRT94L33IB-L
Applications
Network Switches
Interface
Bus
Voltage - Supply
3.14 V ~ 3.47 V
Package / Case
504-LBGA
Mounting Type
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XRT94L33IB-L
Manufacturer:
Exar Corporation
Quantity:
10 000
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XRT94L33
Rev.1.2.0.
CELL DELINEATION ALGORITHM
HEC BYTE VERIFICATION
COSET POLYNOMIAL
CORRECTION MODE
DETECTION MODE
IDLE CELL FILTERING
USER CELL FILTERING
DESCRAMBLING
GFC (GENERIC FLOW CONTROL) EXTRACTION
OAM CELL SUPPORT AND RECEPTION
INTERRUPT SUPPORT FOR THE RECEIVE CELL PROCESSOR BLOCK
2.3.5
The Receive UTOPIA Interface Block complies with “UTOPIA Level 1, 2 and 3” compliant interface to
interconnect the UNI chip to ATM layer or ATM Adaptation Layer processors, operating up to 800 Mbps.
Additionally, the XRT94L33 provides the user with the option of varying the following features associated with
the Receive UTOPIA Bus Interface.
• Operating the UTOPIA Data Bus per the UTOPIA Levels 1, 2 and 3 standards
• Transmit UTOPIA Data Bus width of 8 or 16 bits
• The cell size (e.g., the number of octets being processed per cell via the UTOPIA bus)
• Whether the Receive UTOPIA Clock De-Skewing PLL is enabled or not.
Figure 109 presents a simplistic illustration of the Receive UTOPIA Interface block, along with its external
output pins.
Figure 109 A Simple Illustration of the Receive UTOPIA Interface block
A discussion of the operation of the Receive UTOPIA Bus Interface along with each of these options will be
presented below.
THE PINS OF THE RECEIVE UTOPIA BUS INTERFACE
The ATM Layer Processor will interface to the Receive UTOPIA Interface block via the following pins.
• RxUData[15:0] -
• RxUAddr[4:0] -
• RxUClk
• RxUClkO
• RxUSoC
• RxUPrty
• RxUEnB*
THE RECEIVE UTOPIA INTERFACE BLOCK
Receive UTOPIA Address Bus Input pins
Receive UTOPIA Data Bus Input pins
Receive UTOPIA Interface block clock output pin
Receive UTOPIA Interface block clock input pin
Receive UTOPIA Data Bus – Read Enable Input pin
Receive UTOPIA – Odd Parity Output pin
Receive “Start of Cell” Indicator input pin
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
436
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