XRT94L33IB-L Exar Corporation, XRT94L33IB-L Datasheet - Page 97

• Manufacturer Part Number: XRT94L33IB-L
• Description: IC MAPPER DS3/E3/STS-1 504TBGA
• Manufacturer: Exar Corporation

Specifications of XRT94L33IB-L

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 3.14 V ~ 3.47 V
• Package / Case: 504-LBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

xr
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
AD7
AD8
AE5
RxE1F1E2FP
RxLDCCVAL
RxLDCC
O
O
O
CMOS
CMOS
CMOS
Receive – Line DCC Output Port – DCC Value Indicator Output
pin:
This output pin, along with the “RxTOHClk” and the “RxLDCC”
output pins function as the “Receive Line DCC” output port of the
XRT94L33.
This output pin pulses “High” coincident to when the “Receive Line
DCC” output port outputs a DCC bit via the “RxLDCC” output pin.
This output pin is updated upon the falling edge of “RxTOHClk”.
The Line DCC HDLC Controller circuitry that is interfaced to this
output pin, the “RxLDCC” and the “RxTOHClk” pins is suppose to
do the following.
It should continuously sample and monitor the state of this output
pin upon the rising edge of “RxTOHClk”.
Anytime the “Line DCC HDLC” circuitry samples this output pin
being “HIGH”, it should sample and latch the data on the
“RxLDCC” output pin (as a valid Line DCC bit) into the “Line DCC
HDLC” circuitry.
Receive – Line DCC Output Port – Output Pin:
This output pin, along with “RxLDCCVAL” and the “RxTOHClk”
output pins function as the “Receive Line DCC” output port of the
XRT94L33.
This pin outputs the contents of the Line DCC (e.g., the D4, D5,
D6, D7, D8, D9, D10, D11 and D12 bytes), within the incoming
STS-3 data-stream.
The Receive Line DCC Output port will assert the “RxLDCCVAL”
output pin, in order to indicate that the data, residing on the
“RxLDCC” output pin is a valid Line DCC byte. The Receive Line
DCC output port will update the “RxLDCCVAL” and the “RxLDCC”
output pins upon the falling edge of the “RxTOHClk” output pin.
The Line DCC HDLC circuitry that is interfaced to this output pin,
the “RxLDCCVAL” and the “RxTOHClk” pins is suppose to do the
following.
It should continuously sample and monitor the state of the
“RxLDCCVAL” output pin upon the rising edge of “RxTOHClk”.
Anytime the “Line DCC HDLC” circuitry samples the “RxLDCCVAL”
output pin “HIGH”, it should sample and latch the contents of this
output pin (as a valid Line DCC bit) into the “Line DCC HDLC”
circuitry.
Receive – Order-Wire Output Port – Frame Boundary
Indicator:
This output pin, along with “RxE1F1E2”, “RxE1F1E2Val” and the
“RxTOHClk” output pins function as the “Receive Order-Wire
Output port of the XRT94L33.
This output pin pulses “high” (for one period of “RxTOHClk”)
coincident to when the very first bit (of the E1 byte) is being output
vi the “RxE1F1E2” output pin.
97
XRT94L33
Rev.1.2.0.