XRT94L33IB-L Exar Corporation, XRT94L33IB-L Datasheet - Page 316

• Manufacturer Part Number: XRT94L33IB-L
• Description: IC MAPPER DS3/E3/STS-1 504TBGA
• Manufacturer: Exar Corporation

Specifications of XRT94L33IB-L

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 3.14 V ~ 3.47 V
• Package / Case: 504-LBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

XRT94L33
Rev.1.2.0.
Figure 66 A Simple Illustration of the “External Circuit” being interfaced to the “TxTOH Input Port”
Note:
• Whenever the “external circuit” samples both the “TxTOHEnable_n” and the “TxTOHFrame_n” output pins
“high”, then it should enter a WAIT STATE (e.g., where it will wait for 16 periods of “TxTOHClk_n” to elapse).
Afterwards, the external circuitry should exit this “WAIT STATE” and then place the very first byte (e.g., the
most significant bit) of the “outbound” J0 byte onto the “TxTOH_n” input pin, upon the very next falling edge of
“TxTOHClk_n”. This data bit will be sampled and latched into the “Transmit STS-3 TOH Processor” block
circuitry, upon the very next rising edge of “TxTOHClk_n.
Note:
• Afterwards, the “external circuit” should serially place the remaining seven bits (of the J0 byte) onto the
“TxTOH_n” input pin, upon each of the next seven falling edge of “TxTOHClk_n”.
• The “external circuit” should then revert back to continuously sampling the states of the “TxTOHEnable_n”
and “TxTOHFrame_n” output pins and repeat the above-mentioned process.
Figure 67 presents an illustration of the “TxTOH Input Interface” waveforms, when the “external circuit” is
writing the J0 byte into the “TxTOH Input Port”.
Figure 67 Illustration of the “TxTOH Input Interface” waveforms, when the “External Circuit” is writing
the J0 byte into the “TxTOH Input Port”
2.2.9.5.6
The Transmit STS-3c TOH Processor block permits the user to control the value of the E1 byte which is to be
transmitted via the “outbound” STS-3c data-stream by either or the following options.
• Setting and controlling the E1 byte via software
• Setting and controlling the E1 byte via the “TxPOH Input Port”
The details and instructions for using either of these features are presented below.
2.2.9.5.6.1
The Transmit STS-3c TOH Processor block permits the user to specify the contents of the E1 byte within the
outbound STS-3c data-stream via software command.
The user can configure the Transmit STS-3c TOH Processor block to accomplish this by performing the
following steps.
STEP 1 – Write the value “1” into Bit 4 (E1 Insert Method) within the “Transmit STS-3c Transport –
SONET Transmit Control Register – Byte 1, as depicted below.
Transmit STS-3Transport – SONET Transmit Control Register – Byte 1 (Address = 0x1902)
The step configures the Transmit STS-3c TOH Processor block to read out the contents of the “Transmit
STS-3c Transport – E2 Byte Value Register, and load this value into the E1 byte position within each
outbound STS-3c data-stream.
B
R/O
IT
0
7
The “TxTOHIns_n” line (in Figure 66) is “dashed” because controlling this signal is not necessary if the user has
This “WAIT STATE” period is necessary because the J0 byte is the third byte within the TOH.
Reserved
executed “STEP 1” above.
SUPPORT/HANDLING OF THE E1 BYTE
Setting and Controlling the outbound E1 byte via Software
B
R/O
IT
0
6
E2 Insert
Method
B
R/W
IT
X
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
5
E1 Insert
Method
B
R/W
IT
1
4
316
F1 Insert
Method
B
R/W
IT
X
3
S1 Insert
Method
B
R/W
IT
X
2
K1K2 Insert
Method
B
R/W
IT
X
1
xr
M0M1 Insert
Method[1]
B
R/W
IT
X
0