XRT94L33IB-L Exar Corporation, XRT94L33IB-L Datasheet - Page 272

• Manufacturer Part Number: XRT94L33IB-L
• Description: IC MAPPER DS3/E3/STS-1 504TBGA
• Manufacturer: Exar Corporation

Specifications of XRT94L33IB-L

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 3.14 V ~ 3.47 V
• Package / Case: 504-LBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

XRT94L33
Rev.1.2.0.
STEP 2 – Begin providing the values of the “outbound” J1 byte message to the “TxPOH_n” input port.
The procedure for applying the J1 byte to the “TxPOH_n” input port is presented below.
Using the “TxPOH” Input Port to insert the J1 byte value into the outbound STS-1 SPE data-stream
If the user intends to externally insert the J1 byte into the outbound STS-1 SPE, via the “TxPOH_n” input port,
then they must design some external circuitry (which can be realized in an ASIC, FPGA or CPLD solution) to
do to the following.
• Continuously sample the “TxPOHEnable_n” and the “TxPOHFrame_n” output pins upon the rising edge of
the “TxPOHClk_n” output clock signal.
A simple illustration of this “external circuit” being interfaced to the “TxPOH Input Port” is presented below in
Figure 49.
Figure 49: A Simple Illustration of the “External Circuit” being interfaced to the “TxPOH Input Port”
Note:
• Whenever the “external circuit” samples both the “TxPOHEnable_n” and “TxPOHFrame_n” output pins
“high”, then it should place the very first bit (e.g., the most significant bit) of the “outbound” J1 byte onto the
“TxPOH_n” input pin, upon the very next falling edge of “TxPOHClk_n”. This data bit will be sampled and
latched into the “Transmit SONET POH Processor” block circuitry, upon the very next rising edge of
“TxPOHClk_n”.
• Afterwards, the “external circuit” should serially place the remaining seven bits (of the J1 byte) onto the
“TxPOH_n” input pin, upon each of the next seven falling edges of “TxPOHClk_n”.
• The “external circuit” should then revert back to continuously sampling the states of the “TxPOHEnable_n”
and “TxPOHFrame_n” output pins and repeat the above-mentioned process.
The “TxPOHIns_n” line (in Figure 49) is “dashed” because controlling this signal is not necessary if the user has
executed “STEP 1” above.
XRT95L34 Device
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
TxPOHEnable_n
TxPOHFrame_n
TxPOHClk_n
TxPOHIns_n
TxPOH_n
272
TxPOHData_OUT
TxPOHFrame_IN
TxPOHEnable_IN
TxPOH_INSERT
TxPOHClk_IN
External Circuit
xr