XRT94L33IB-L Exar Corporation, XRT94L33IB-L Datasheet - Page 196

• Manufacturer Part Number: XRT94L33IB-L
• Description: IC MAPPER DS3/E3/STS-1 504TBGA
• Manufacturer: Exar Corporation

Specifications of XRT94L33IB-L

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 3.14 V ~ 3.47 V
• Package / Case: 504-LBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

XRT94L33
Rev.1.2.0.
Conversely, if Bit 3 is set to “0”, then the “Transmit Cell Extraction Buffer” does not contain an ATM cell that
needs to be read. At this point, the Microprocessor Interface should continue to poll the state of this bit-field
and wait until this bit-field toggles to “1”.
Executing STEP 2 using the Interrupt-Driven Approach
In order to reduce or eliminate the Microprocessor Overhead of continuously polling the state of Bit 3, the user
can use the “Transmit Cell Extraction” Interrupt feature, within the chip. If the Microprocessor invokes this
feature, then the XRT94L33 will generate an interrupt anytime a new cell has been received and loaded into
the “Transmit Cell Extraction Buffer”.
The user can enable the “Cell Extraction” Interrupt by setting Bit 5 (Cell Extraction Interrupt Enable), within the
“Transmit ATM Cell Processor – Interrupt Enable” Register to “1” as indicated below.
Transmit ATM Cell Processor – Interrupt Enable Register (Address = 0xNF0F)
Once the “Cell Extraction Buffer” receives a “COPIED” cell from the “Transmit User Cell Filter”, then the
XRT94L33 will do all of the following:
• It will toggle the “INT*” output pin “LOW”.
• It will set Bit 5 (Cell Extraction Interrupt Status) within the Transmit ATM Cell Processor – Interrupt Status
Register, to “1” as depicted below.
Transmit ATM Cell Processor – Interrupt Status Register (Address = 0xNF0B)
At this point, the user can now proceed onto STEP 3.
STEP 3 – Read out the very first 32-bit word of this new ATM cell from the “Transmit Cell Extraction
Buffer”.
This is accomplished by executing the following four sub-steps.
STEP 3a – Read the contents of the first byte (of this newly received ATM cell) from the “Transmit
ATM Cell – Insertion/Extraction Memory Register – Byte 3; as depicted below.
B
B
R/O
R/O
IT
IT
0
0
7
7
Unused
Unused
B
B
R/O
R/O
IT
IT
0
0
6
6
Extraction
Extraction
Interrupt
Interrupt
Enable
Status
B
B
RUR
R/W
Cell
Cell
IT
IT
1
1
5
5
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
Insertion
Insertion
Interrupt
Interrupt
Enable
Status
B
B
RUR
R/W
Cell
Cell
IT
IT
0
0
4
4
196
Extraction
Extraction
Overflow
Overflow
Interrupt
Interrupt
Memory
Memory
Enable
Status
B
B
RUR
R/W
Cell
Cell
IT
IT
0
0
3
3
Cell Insertion
Cell Insertion
Overflow
Overflow
Interrupt
Interrupt
Memory
Memory
Enable
Status
B
B
RUR
R/W
IT
IT
0
0
2
2
Detection of
Detection of
HEC Byte
HEC Byte
Interrupt
Interrupt
Enable
Status
B
Error
B
Error
RUR
R/W
IT
IT
0
0
1
1
xr
Detection of
Detection of
Parity Error
Parity Error
Interrupt
Interrupt
Enable
Status
B
B
RUR
R/W
IT
IT
0
0
0
0