XRT94L33IB-L Exar Corporation, XRT94L33IB-L Datasheet - Page 360

• Manufacturer Part Number: XRT94L33IB-L
• Description: IC MAPPER DS3/E3/STS-1 504TBGA
• Manufacturer: Exar Corporation

Specifications of XRT94L33IB-L

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 3.14 V ~ 3.47 V
• Package / Case: 504-LBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

XRT94L33
Rev.1.2.0.
•
If the Receive STS-3 TOH Processor block detects any B2 byte errors, then it will do the following.
Receive STS-3 Transport Interrupt Status Register – Byte 0 (Address = 0x110B)
Note:
2.3.1.12.1
The user can configure the Receive STS-3 TOH Processor block to increment the “Receive STS-3 Transport
B2 Byte Error Count” Register, by the value “1” for each STS-3 frame that it determined to have at least one
bit-error within the B2 bytes.
The user can accomplish this by setting Bit 1 (B2 Error Type), within the “Receive STS-3 Transport Control
Register – Byte 0” to “1”, as illustrated below.
Receive STS-3 Transport Control Register – Byte 0 (Address = 0x1103)
2.3.1.12.2
The user can configure the Receive STS-3 TOH Processor block to increment the “Receive STS-3 Transport
B2 Error Count” Register by the number of “B2 bits, which are determined to be in error. Therefore, in this
mode, it is possible for the Receive STS-3 TOH Processor block to increment this register by as much as the
value of “24” for each STS-3 frame.
The user can accomplish this by setting Bit 1 (B2 Error Type) within the “Receive STS-3 Transport Control
Register – Byte 0” to “0”, as illustrated below.
Change of
SF Defect
Condition
Interrupt
Unused
Status
B
B
RUR
R/O
This resulting BIP-8 value will be compared with the contents of the B2 byte, within the very next “newly
received” STS-3 frame.
IT
IT
0
0
7
7
The Receive STS-3 TOH Processor block will increment these registers either by the number of erred STS-3
frames detected, or by the number of B2 bits that are detected to be in error (within a given STS-3 frame),
depending upon user selection, as described below.
o
o
Configuring the Receive STS-3 TOH Processor block to increment the “Receive STS-3
Transport B2 Error Count” register on a “per-Frame” basis.
Configuring the Receive STS-3 TOH Processor block to increment the “Receive STS-3
Transport B2 Error Count” register on a “per B2 bit error” basis
SF Detect
Change of
SD Defect
Condition
Interrupt
Enable
It will generate the “Detection of B2 Byte Error” Interrupt, by toggling the “INT*” output pin
“LOW” and by setting Bit 4 (Detection of B2 Byte Error Interrupt Status) within the “Receive
STS-3 Transport Interrupt Status” Register to “1”, as indicated below.
It will increment the “Receive STS-3 Transport B2 Byte Error Count” registers. The “Receive
STS-3 Transport B2 Byte Error Count” register is actually a 32 bit register that resides at
Address Locations 0x1114 through 0x1117.
Status
B
R/W
B
RUR
IT
0
IT
0
6
6
Detection of
SD Detect
REI-L Error
Interrupt
Enable
Status
B
R/W
B
RUR
IT
0
IT
0
5
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
5
Descramble
Detection of
Disable
Interrupt
B2 Byte
Status
B
R/W
B
Error
RUR
IT
0
IT
1
4
4
360
SDH/SONET*
Detection of
Interrupt
B1 Byte
Status
B
Error
RUR
B
R/W
IT
0
IT
0
3
3
LOF Defect
Change of
REI-L Error
Condition
Interrupt
Status
B
RUR
Type
B
R/W
IT
0
IT
0
2
2
SEF Defect
Change of
Condition
Interrupt
B2 Error
Status
B
RUR
B
Type
R/W
IT
0
IT
1
1
xr
1
LOS Defect
Change of
Condition
Interrupt
B1 Error
Status
B
RUR
Type
B
R/W
IT
IT
0
0
0
0