XRT94L33IB-L Exar Corporation, XRT94L33IB-L Datasheet - Page 372

• Manufacturer Part Number: XRT94L33IB-L
• Description: IC MAPPER DS3/E3/STS-1 504TBGA
• Manufacturer: Exar Corporation

Specifications of XRT94L33IB-L

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 3.14 V ~ 3.47 V
• Package / Case: 504-LBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

XRT94L33
Rev.1.2.0.
1. The “Interval” SF Detector will accumulate B2 errors over a much greater amount of time (e.g., 8 times
greater) than that of the “Burst” SF Detector; when determine whether to declare/clear the SF condition, or
not.
2. The “Interval” SF Detector permits a “user-defined” hysteresis between the conditions required to declare
and clear the SF condition. The “Burst” SF Detector permits no hysteresis between the conditions required to
declare and clear the SF condition.
2.3.1.14.1
The Receive STS-3 TOH Processor block can be configured to tally B2 errors in one of two-different
manners.
• On a “per-bit” basis
• On a “per-frame” basis
If the user configures the Receive STS-3 TOH Processor block to “tally” B2 errors on a “per-bit” basis, then it
will declare an error for each bit (within the incoming B2 byte) that is determined to be in error. In this case,
the Receive STS-3 TOH Processor block can declare as many as 8 B2 errors, per STS-3 frame (e.g., when
all 8 bit, within the incoming B2 byte, are in error).
Conversely, if the user configures the Receive STS-3 TOH Processor block to “tally” B2 errors on a “per-
frame” basis, then it will declare a single B2 error, anytime an incoming B2 byte is determined to be in error.
In this case, the Receive STS-3 TOH Processor block will only declare as many as 1 B2 error, per STS-3
frame.
The user can configure the Receive STS-3 TOH Processor block to “tally” B2 errors on a “per-bit” basis, by
setting Bit 1 (B2 Error Type), within the “Receive STS-3 Transport Control Register – Byte 0” to “0”, as
depicted below.
Receive STS-3 Transport Control Register – Byte 0 (Address = 0x1103)
Likewise, the user can configure the Receive STS-3 TOH Processor block to “tally” B2 errors on a “per-frame”
basis, by setting Bit 1 (B2 Error Type) to “1”, as depicted below.
Receive STS-3 Transport Control Register – Byte 0 (Address = 0x1103)
This configuration option, on how the Receive STS-3 TOH Processor block “tallies” B2 errors impacts the
following functions.
• The SF Declaration and Clearance Criteria
• The SD Declaration and Clearance Criteria
• The values that the corresponding Transmit STS-3 TOH Processor block, will transmit to the remote
terminal, via the REI-L bit-fields (within the M0 byte).
Unused
Unused
B
R/O
B
R/O
IT
0
IT
0
7
7
SF Detect
The Definition of B2 Errors
Enable
SF Detect
B
R/W
Enable
IT
0
B
R/W
IT
6
0
6
SD Detect
Enable
B
R/W
SD Detect
IT
0
Enable
B
5
R/W
IT
0
5
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
Descramble
Disable
B
R/W
Descramble
IT
0
Disable
4
B
R/W
IT
0
4
SONET*
372
SDH/
B
R/W
IT
0
SDH/SONET*
3
B
R/W
IT
0
3
Error Type
REI-L
B
R/W
IT
0
2
REI-L Error
Type
B
R/W
IT
0
B2 Error
2
B
Type
R/W
IT
1
1
B2 Error
B
Type
R/W
B1 Error
IT
0
B
Type
xr
1
R/W
IT
0
0
B1 Error
Type
B
R/W
IT
0
0