XRT94L33IB-L Exar Corporation, XRT94L33IB-L Datasheet - Page 241

• Manufacturer Part Number: XRT94L33IB-L
• Description: IC MAPPER DS3/E3/STS-1 504TBGA
• Manufacturer: Exar Corporation

Specifications of XRT94L33IB-L

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 3.14 V ~ 3.47 V
• Package / Case: 504-LBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
Transmit STS-3c Path – Transmit H4 Byte Value Register (Address = 0x19A7)
2.2.7.3.7.2
The Transmit STS-3c POH Processor block permits the user to specify the contents of the H4 byte, within the
“outbound” STS-3c SPE, via data applied to the “TxPOH_n” input pin.
The user can configure the Transmit STS-3c POH Processor block to accomplish this by performing the
following steps.
STEP 1 – Write the value “1” into Bit 0 (F2 Byte Insertion Type) within the “Transmit STS-3c Path –
SONET Control Register – Byte 1”, as depicted below.
Transmit STS-3c Path – SONET Control Register – Byte 1 (Address = 0x1982)
This step configures the Transmit STS-3c POH Processor block to use the “TxPOH_n” input port as the
source for the H4 byte, within each “outbound” STS-3c SPE. In this mode, the Transmit STS-3c POH
Processor block will accept the value, corresponding to the H4 byte (via the “TxPOH_n” input port) and it will
write this data into the H4 byte position, within the “outbound” STS-3c SPE.
STEP 2 – Begin providing the values of the “outbound” H4 byte to the “TxPOH_n” input port.
The procedure for applying the H4 byte to the “TxPOH_n” input port is presented below.
Using the “TxPOH” Input Port to insert the H4 byte value into the outbound STS-3c SPE data-stream
If the user intends to externally insert the H4 byte into the outbound STS-3c SPE, via the “TxPOH_n” input
port, then they must design some external circuitry (which can be realized in an ASIC, FPGA or CPLD
solution) to do to the following.
• Continuously sample the “TxPOHEnable_n” and the “TxPOHFrame_n” output pins upon the rising edge of
the “TxPOHClk_n” output clock signal.
A simple illustration of this “external circuit” being interfaced to the “TxPOH Input Port” is presented below in
B
B
R/W
R/O
IT
IT
0
0
7
7
Setting and Controlling the Outbound H4 Byte via the “TxPOH_n Input Port”
B
B
R/W
R/O
IT
IT
0
0
6
6
Unused
B
B
R/W
R/O
IT
IT
0
0
5
5
Transmit_H4_Byte_Value[7:0]
B
B
R/W
R/O
IT
IT
0
0
4
4
241
Z5 Insertion
B
B
Type
R/W
R/W
IT
IT
0
0
3
3
Z4 Insertion
Type
B
B
R/W
R/W
IT
IT
0
0
2
2
Z3 Insertion
B
B
Type
R/W
R/W
IT
IT
0
0
1
1
XRT94L33
H4 Insertion
Rev.1.2.0.
B
B
Type
R/W
R/W
IT
IT
0
1
0
0