XRT94L33IB-L Exar Corporation, XRT94L33IB-L Datasheet - Page 198

• Manufacturer Part Number: XRT94L33IB-L
• Description: IC MAPPER DS3/E3/STS-1 504TBGA
• Manufacturer: Exar Corporation

Specifications of XRT94L33IB-L

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 3.14 V ~ 3.47 V
• Package / Case: 504-LBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

XRT94L33
Rev.1.2.0.
2.2.6.10
The Transmit ATM Cell Processor block consists of a “Idle Cell Generator” block. Figure 28 presents the
functional block diagram of the “Transmit ATM Cell Processor block with the “Idle Cell Generator” block
highlighted.
Figure 28: Illustration of the Transmit ATM Cell Processor block Functional Block Diagram, with the
“Idle Cell Generator” block highlighted
Whenever the TxFIFO (within the Transmit UTOPIA Interface block) does not contain a complete cell, the
Transmit ATM Cell Processor will first read out any ATM cell data that resides within the “Transmit Cell
Insertion Buffer” and will insert this (or these) ATM cells into the “Transmit Data Path”. Once both the
“TxFIFO” and the “Transmit Cell Insertion Buffer” are depleted, then the Transmit ATM Cell Processor block
will automatically fill in the STS-3 SPE bandwidth by generating and transmitting Idle Cells via the “Transmit
Data Path”. By default, the Transmit ATM Cell Processor block will generate Idle Cells that contain header
byte patterns which conform to the ATM Forum recommendations. However, the XRT94L33 does contain
some registers that permit the user to “customize” the header byte and payload byte pattern of these Idle
cells.
“customized” header and payload bytes is presented below.
The Procedure for configuring the Transmit ATM Cell Processor Block to transmit Idle Cells with
“user-specified” header and payload bytes
The user can configure the Transmit ATM Cell Processor block to generate and transmit Idle Cells with “user-
specified” header and payload bytes, by executing the following steps.
The procedure for configuring the Idle Cell Generator to generate and transmit Idle Cells with
Transmit UTOPIA
T
Interface Block
HE
TxFIFO
TxFIFO
I
DLE
Main Data Path
C
ELL
G
ENERATOR
Generator
Checker
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
Generator
Checker
Parity
Idle Cell
Block
Parity
Idle Cell
Block
User Cell
Calculation
HEC Byte
User Cell
Calculation
Insertion
HEC Byte
Filter
Block
Insertion
198
Filter
Block
Block
Block
&
&
Cell Extraction
Cell Insertion
Cell Extraction
Transmit GFC
Cell Insertion
Cell Payload
Processor
Processor
Transmit GFC
Nibble-Field
Cell Payload
Scrambler
Processor
Processor
Buffer/
Nibble-Field
Input Port
Buffer/
Scrambler
Buffer/
Buffer/
Input Port
Block
Block
Block
Block
Microprocessor
Microprocessor
Processor Block
SONET/STS-3c
To Transmit
Interface
Input Port
Interface
TxGFC
Block
Block
POH
xr