XRT94L33IB-L Exar Corporation, XRT94L33IB-L Datasheet - Page 64

• Manufacturer Part Number: XRT94L33IB-L
• Description: IC MAPPER DS3/E3/STS-1 504TBGA
• Manufacturer: Exar Corporation

Specifications of XRT94L33IB-L

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 3.14 V ~ 3.47 V
• Package / Case: 504-LBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

XRT94L33
Rev.1.2.0.
A23
TXHDLCDAT_4_1
TXDS3OHIND_1
STS1TXA_D4_1
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
I/O
TTL/CMOS
Transmit STS-1 Telecom Bus – Channel 1 – Input Data
Bus pin number 4:
The exact function of this pin depends upon whether the STS-
1 Telecom Bus Interface, associated with Channel 1 is
enabled or not.
If STS-1 Telecom Bus (Channel 1) has been enabled –
STS-1 Transmit Telecom Bus – Input Data Bus pin number 4:
STS1TXA_D4_1:
This
“STS1TXA_D_1[3:0] function as the “STS-1 Transmit (Add)
Telecom Bus – Input Data Bus for Channel 1. The STS-1
Telecom Bus interface will sample and latch this pin upon the
falling edge of “STS1TXA_CK_1”.
If STS-1 Telecom Bus (Channel 1) has NOT been enabled:
If STS-1 Telecom Bus (Channel 1) has not been enabled, then
this particular pin can be configured to function in either of the
following roles
TXHDLCDAT_4_1 (Transmit HDLC block data – Channel 1
– Input data pin 4)
This input pin will function as a part of the “Transmit HDLC
Controller” byte-wide data input bus, whenever the user
configures the DS3/E3 Framer block (associated with Channel
1) to operate in the “High-Speed HDLC Controller” Mode. This
pin will function as Data Input Pin # 4.
TXDS3OHIND_1 (Transmit DS3 Overhead Indicator –
Channel 1)
This output pin will pulse “high” one bit-period prior to the time
that the DS3/E3 Frame Generator block (within Channel 1) will
be processing an Overhead bit. The purpose of this outpout
pin is to warn the Terminal Equipment that, during the very
next bit-period, the DS3/E3 Frame Generator block is going to
be processing an Overhead Bit and will be ignoring any data
that is applied to to the TxSer input pin.
NOTE: The user can ignore this output pin provide that that
64
input
either the Primary or Secondary Frame Synchronizer
block is always “up-stream” from the DS3/E3 Frame
Generator block.
pin
along
with
“STS1TXA_D_1[7:5]”
xr
and