XRT94L33IB-L Exar Corporation, XRT94L33IB-L Datasheet - Page 125

• Manufacturer Part Number: XRT94L33IB-L
• Description: IC MAPPER DS3/E3/STS-1 504TBGA
• Manufacturer: Exar Corporation

Specifications of XRT94L33IB-L

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 3.14 V ~ 3.47 V
• Package / Case: 504-LBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
Table 1 Description of the Microprocessor Interface Pins whenever the Microprocessor Interface has
been configured to operate in the Intel Asynchronous Mode
The XRT94L33 supports a wide variety of Microprocessor types, including Intel and Motorola types of
Microprocessors. When the Microprocessor Interface is operating in the “Motorola” mode, then some
of the control signals function in a manner as required by the Motorola 68000 family of
microprocessors. Likewise, when the Microprocessor Interface is operating in the “Intel” Mode, then
some of these Control Signals function in a manner as required by the Intel 80xx family of
microprocessorsTable 2 lists and describes those Microprocessor Interface signals whose role is
P
WR_RW
ALE_AS
RD_DS
A[15:0]
IN
D[7:0]
INT*
CS*
N
AME
P
IN
#
T
I/O
YPE
O
I
I
I
I
I
Bi-directional data bus Input/Output pins for on-chip register and buffer
READ or WRITE operation.
This byte-wide data bus carries all data that is being written into or read form the
XRT94L33.
Sixteen Bit Address Bus Input pins:
This 16-bit Address Bus permits the user to select an on-chip register or buffer
location to be the “target” address for the current READ or WRITE operation.
Chip Select Input Pin:
This “active-low” signal selects the Microprocessor Interface of the XRT94L33 and
enables READ/WRITE operations with on-chip registers and buffer locations.
Interrupt Request Output Pin:
This
Microprocessor/Microcontroller that the XRT94L33 has a pending interrupt request.
Under normal conditions this output pin will be at a logic “high” level. However, this
output pin will toggle “low” whenever the XRT94L33 has a pending interrupt
request that needs servicing. This output pin will remain “low” until all pending
interrupt requests have been serviced.
Please see Section _ for more information on servicing interrupts.
Address-Latch Enable:
This “active-high” signal is used to latch the contents on the address bus, A[15:0].
The contents of the Address Bus are latched into the A[15:0] inputs on the falling
edge of ALE_AS.
The contents of the Address Bus will only be latched into the XRT94L33 circuitry if
the CS* input pin is asserted (e.g., pulled “low”).
Read Strobe Signal:
This “active-low” input functions as the read signal from the local µP. When this
signal goes “low”, the XRT94L33 Microprocessor Interface will respond by placing
the contents of the addressed register on the Data Bus pins (D[7:0]). The Data
Bus will be “tri-stated” once this input signal returns “high”.
Write Strobe Signal:
This “active-low” input functions as the write signal from the local µP. The contents
of the Data Bus (D[7:0]) will be written into the addressed register (via A[15:0]), on
the rising edge of this signal.
open-drain/active-low
125
output
D
ESCRIPTION
signal
will
inform
XRT94L33
the
Rev.1.2.0.
local