XRT94L33IB-L Exar Corporation, XRT94L33IB-L Datasheet - Page 228

• Manufacturer Part Number: XRT94L33IB-L
• Description: IC MAPPER DS3/E3/STS-1 504TBGA
• Manufacturer: Exar Corporation

Specifications of XRT94L33IB-L

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 3.14 V ~ 3.47 V
• Package / Case: 504-LBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

XRT94L33
Rev.1.2.0.
Setting this bit-field to “0” configures the Transmit STS-3c POH Processor block to set the REI-P bit-fields
(within the G1 byte of the “outbound” STS-3c SPE); to a value the reflects the number of bits (within the B3
byte) that were determined to be in error (within the most recently received STS-3c SPE) by the
corresponding Receive STS-3c POH Processor block. In this case, the REI-P bit-fields can range in value
from “0” (for no B3 bit errors) to “8” (for all B3 bits being in error).
Setting this bit-field to “1” configures the Transmit STS-3c POH Processor block to set the REI-P bit-fields
(within the G1 byte of the ‘outbound”STS-3c SPE); to a value that indicates whether or not at least one B3
byte error was detected within the most recently received STS-3c SPE; by the corresponding Receive STS-3c
POH Processor block. In this mode, the Transmit STS-3c POH Processor block will set the “REI-P” bit-fields
(within the outbound STS-3c SPE) to “0” if the corresponding “Receive STS-3c POH Processor” block is not
detecting any B3 byte errors, in its incoming STS-3c data-stream. Conversely, the Transmit STS-3c POH
Processor block will set the “REI-P” bit-fields (within the “outbound” STS-3c SPE) to “1” if the corresponding
Receive STS-3c POH Processor block receives an STS-3c SPE that contains a B3 byte error.
2.2.7.3.3.2
The user can configure the Transmit STS-3c POH Processor block to transmit the REI-P indicator (per
software command) by executing the following steps.
STEP 1- Write the value “[0, 1]” into Bits 5 and 6 (REI-P Insertion Type[1:0]) within the “Transmit STS-
3c Path SONET Control Register – Byte 0”; as depicted below.
Transmit STS-3c Path – SONET Control Register – Byte 0 (Address = 0x1983)
This step configures the “Transmit STS-3c POH Processor” block to automatically read out the contents of
Bits 4 through 7 (of the Transmit STS-3c Path – G1 Byte Value” register) and write the value of these bits into
bits 1 through 4 (of the G1 byte) within the “outbound” STS-3c SPE. The bit-format of the “Transmit STS-3c
Path – G1 Byte Value” register (with the appropriate bits “shaded”) is presented below.
Transmit STS-3c Path – Transmit G1 Byte Value Register (Address = 0x199F)
In this mode, the user can transmit an “un-erred” REI-P value by setting Bits 4 through 7 (within the Transmit
STS-3c Path – Transmit G1 Byte Value” register) to [0, 0, 0, 0]. Conversely, the user can transmit an “erred”
REI-P value by setting Bits 4 through 7 (within the Transmit STS-3c Path – Transmit G1 Byte Value” register)
to some value between 1 and 8.
F2 Insertion
B
Type
B
R/W
R/W
IT
IT
0
0
7
7
REI-P Insertion Type[1:0]
Configuring the Transmit STS-3c POH Processor block to transmit the REI-P Indicator,
upon software control
B
B
R/W
R/W
IT
IT
0
0
6
6
B
B
R/W
R/W
IT
IT
1
0
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
5
5
Transmit_G1_Byte_Value[7:0]
RDI-P Insertion Type[1:0]
B
B
R/W
R/W
IT
IT
0
0
4
4
228
B
B
R/W
R/W
IT
IT
X
0
3
3
Insertion
C2 Byte
B
Type
B
R/W
R/W
IT
IT
X
0
2
2
Auto Insert
C2 Byte
Enable
Mode
B
B
R/W
R/W
IT
IT
X
0
1
1
xr
Transmit
Enable
AIS-P
B
B
R/W
R/W
IT
IT
0
0
0
0