DK-DEV-5M570ZN Altera, DK-DEV-5M570ZN Datasheet - Page 11

• Manufacturer Part Number: DK-DEV-5M570ZN
• Description: KIT DEV MAX V 5M570Z
• Manufacturer: Altera
• Series: MAX® Vr
• Type: CPLDr

Specifications of DK-DEV-5M570ZN

• Contents: Board, Cable(s), Software and Documentation
• Silicon Manufacturer: Altera
• Core Architecture: CPLD
• Core Sub-architecture: MAX
• Silicon Core Number: 5M
• Silicon Family Name: MAX V
• Kit Contents: MAX V CPLD Development Board, USB Cable
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: 5M570ZF256
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2722

Chapter 1: MAX V Device Family Overview
Integrated Software Platform
Table 1–2. MAX V Packages and User I/O Pins
Table 1–3. MAX V Package Sizes
Integrated Software Platform
Device Pin-Outs
January 2011 Altera Corporation
5M40Z
5M80Z
5M160Z
5M240Z
5M570Z
5M1270Z
5M2210Z
Note to
(1) Device packages under the same arrow sign have vertical migration capability.
Pitch (mm)
Area (mm
Length × width
(mm × mm)
Device
Package
Table
2
)
1–2:
f
f
f
64-Pin
MBGA
4.5 × 4.5
30
30
—
—
—
—
—
64-Pin
MBGA
20.25
the necessary power pins for migration. For I/O pin migration across densities, cross
reference the available I/O pins using the device pin-outs for all planned densities of
a given package type to identify which I/O pins can be migrated. The Quartus
software can automatically cross-reference and place all pins for you when given a
device migration list.
The Quartus II software provides an integrated environment for HDL and schematic
design entry, compilation and logic synthesis, full simulation and advanced timing
analysis, and programming of MAX V devices.
For more information about the Quartus II software features, refer to the
Handbook.
You can debug your MAX V designs using In-System Sources and Probes Editor in
the Quartus II software. This feature allows you to easily control any internal signal
and provides you with a completely dynamic debugging environment.
For more information about the In-System Sources and Probes Editor, refer to the
Design Debugging Using In-System Sources and Probes
Handbook.
For more information, refer to the
0.5
64-Pin
EQFP
54
54
54
—
—
—
—
64-Pin
EQFP
7 × 7
0.4
49
68-Pin
MBGA
(Note 1)
68-Pin
—
52
52
52
—
—
—
MBGA
5 × 5
0.5
25
100-Pin
TQFP
100-Pin
14 × 14
—
79
79
79
74
—
—
TQFP
196
0.5
MAX V Device Pin-Out Files
100-Pin
MBGA
100-Pin
MBGA
6 × 6
—
—
79
79
74
—
—
0.5
36
chapter of the Quartus II
144-Pin
144-Pin
20 × 20
TQFP
TQFP
114
114
114
400
—
—
—
—
0.5
page.
256-Pin
256-Pin
17 × 17
FBGA
FBGA
159
211
203
289
—
—
—
—
MAX V Device Handbook
1
Quartus II
324-Pin
324-Pin
19 × 19
FBGA
FBGA
®
271
271
361
—
—
—
—
—
1
II
1–3