DK-DEV-5M570ZN Altera, DK-DEV-5M570ZN Datasheet - Page 76

• Manufacturer Part Number: DK-DEV-5M570ZN
• Description: KIT DEV MAX V 5M570Z
• Manufacturer: Altera
• Series: MAX® Vr
• Type: CPLDr

Specifications of DK-DEV-5M570ZN

• Contents: Board, Cable(s), Software and Documentation
• Silicon Manufacturer: Altera
• Core Architecture: CPLD
• Core Sub-architecture: MAX
• Silicon Core Number: 5M
• Silicon Family Name: MAX V
• Kit Contents: MAX V CPLD Development Board, USB Cable
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: 5M570ZF256
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2722

3–28
Figure 3–6. JTAG Timing Waveform for MAX V Devices
Table 3–41. JTAG Timing Parameters for MAX V Devices (Part 1 of 2)
MAX V Device Handbook
t
t
t
t
t
t
t
t
t
t
t
t
JCP
JCH
JCL
JPSU
JPH
JPCO
JPZX
JPXZ
JSSU
JSH
JSCO
JSZX
(1)
Symbol
JTAG Timing Specifications
Captured
Figure 3–6
family.
Table 3–41
TCK clock period for V
TCK clock period for V
TCK clock period for V
TCK clock period for V
TCK clock high time
TCK clock low time
JTAG port setup time
JTAG port hold time
JTAG port clock to output
JTAG port high impedance to valid output
JTAG port valid output to high impedance
Capture register setup time
Capture register hold time
Update register clock to output
Update register high impedance to valid output
Driven
Signal
Signal
to be
to be
TMS
TDO
TCK
TDI
shows the timing waveform for the JTAG signals for the MAX V device
lists the JTAG timing parameters and values for the MAX V device family.
t
JCH
t
JPZX
t
JSZX
t
JCP
t
JSSU
CCIO1
CCIO1
CCIO1
CCIO1
(2)
t
Parameter
JCL
(2)
= 3.3 V
= 2.5 V
= 1.8 V
= 1.5 V
t
JSH
t
t
JPCO
JSCO
t
JPSU
(2)
(2)
Chapter 3: DC and Switching Characteristics for MAX V Devices
t
JSXZ
t
JPH
t
55.5
62.5
JPXZ
Min
100
143
20
20
10
—
—
—
10
—
—
8
8
January 2011 Altera Corporation
Timing Model and Specifications
Max
—
—
—
—
—
—
—
—
15
15
15
—
—
25
25
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns