DK-DEV-5M570ZN Altera, DK-DEV-5M570ZN Datasheet - Page 85
![KIT DEV MAX V 5M570Z](/photos/18/31/183180/dk-dev-5m570zn_sml.jpg)
DK-DEV-5M570ZN
Manufacturer Part Number
DK-DEV-5M570ZN
Description
KIT DEV MAX V 5M570Z
Manufacturer
Altera
Series
MAX® Vr
Type
CPLDr
Datasheets
1.DK-DEV-5M570ZN.pdf
(30 pages)
2.DK-DEV-5M570ZN.pdf
(2 pages)
3.DK-DEV-5M570ZN.pdf
(30 pages)
4.DK-DEV-5M570ZN.pdf
(164 pages)
5.DK-DEV-5M570ZN.pdf
(24 pages)
Specifications of DK-DEV-5M570ZN
Contents
Board, Cable(s), Software and Documentation
Silicon Manufacturer
Altera
Core Architecture
CPLD
Core Sub-architecture
MAX
Silicon Core Number
5M
Silicon Family Name
MAX V
Kit Contents
MAX V CPLD Development Board, USB Cable
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
5M570ZF256
Lead Free Status / Rohs Status
Compliant
Other names
544-2722
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Chapter 4: Hot Socketing and Power-On Reset in MAX V Devices
Power-On Reset Circuitry
Figure 4–4. ESD Protection During Negative Voltage Zap
Power-On Reset Circuitry
December 2010 Altera Corporation
Power-Up Characteristics
When the I/O pin receives a negative ESD zap at the pin that is less than –0.7 V (0.7 V
is the voltage drop across a diode), the intrinsic
P-Substrate/N+ drain diode is forward biased. Therefore, the discharge ESD current
path is from GND to the I/O pin, as shown in
MAX V devices have POR circuits to monitor the V
during power up. The POR circuit monitors these voltages, triggering download from
the non-volatile configuration flash memory block to the SRAM logic, maintaining the
tri-state of the I/O pins (with weak pull-up resistors enabled) before and during this
process. When the MAX V device enters user mode, the POR circuit releases the I/O
pins to user functionality. The POR circuit of the MAX V device does not monitor the
V
When power is applied to a MAX V device, the POR circuit monitors V
begins SRAM download at 1.55 V for MAX V devices. From this voltage reference, the
SRAM download and entry into user mode takes 200 to 450 µs maximum, depending
on your device density. This period of time is specified as t
timing section of the
Entry into user mode is gated by whether all the V
sufficient operating voltage. If V
device enters user mode within the t
than t
banks are powered.
CCINT
CONFIG
voltage level after the device enters into user mode.
I/O
after V
CCINT
GND
DC and Switching Characteristics for MAX V Devices
Source
Drain
Drain
Source
, the device does not enter user mode until 2 µs after all V
PMOS
NMOS
CCINT
Gate
Gate
CONFIG
and V
P-Substrate
specifications. If V
CCIO
Figure
N+
N+
are powered simultaneously, the
CCIO
D
S
CCINT
GND
I/O
G
4–4.
banks are powered with
and V
CONFIG
CCIO
CCIO
in the power-up
is powered more
voltage levels
MAX V Device Handbook
CCINT
chapter.
and
CCIO
4–5
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