DK-DEV-5M570ZN Altera, DK-DEV-5M570ZN Datasheet - Page 17

• Manufacturer Part Number: DK-DEV-5M570ZN
• Description: KIT DEV MAX V 5M570Z
• Manufacturer: Altera
• Series: MAX® Vr
• Type: CPLDr

Specifications of DK-DEV-5M570ZN

• Contents: Board, Cable(s), Software and Documentation
• Silicon Manufacturer: Altera
• Core Architecture: CPLD
• Core Sub-architecture: MAX
• Silicon Core Number: 5M
• Silicon Family Name: MAX V
• Kit Contents: MAX V CPLD Development Board, USB Cable
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: 5M570ZF256
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2722

Chapter 2: MAX V Architecture
Logic Array Blocks
Figure 2–3. LAB Structure for MAX V Devices
Note to
(1) Only from LABs adjacent to IOEs.
December 2010 Altera Corporation
Fast I/O connection
to IOE (1)
DirectLink
interconnect from
adjacent LAB
or IOE
DirectLink
interconnect to
adjacent LAB
or IOE
Figure
2–3:
adjacent LE for fast sequential LUT connections within the same LAB. Register chain
connections transfer the output of one LE’s register to the adjacent LE’s register
within an LAB. The Quartus
adjacent LABs, allowing the use of local, LUT chain, and register chain connections
for performance and area efficiency.
Logic Element
LE0
LE1
LE2
LE3
LE4
LE5
LE6
LE7
LE8
LE9
LAB
®
II software places associated logic within an LAB or
Figure 2–3
Local Interconnect
Row Interconnect
shows the MAX V LAB.
MAX V Device Handbook
Column Interconnect
Fast I/O connection
to IOE (1)
DirectLink
interconnect from
adjacent LAB
or IOE
DirectLink
interconnect to
adjacent LAB
or IOE
2–5