DK-DEV-5M570ZN Altera, DK-DEV-5M570ZN Datasheet - Page 150

• Manufacturer Part Number: DK-DEV-5M570ZN
• Description: KIT DEV MAX V 5M570Z
• Manufacturer: Altera
• Series: MAX® Vr
• Type: CPLDr

Specifications of DK-DEV-5M570ZN

• Contents: Board, Cable(s), Software and Documentation
• Silicon Manufacturer: Altera
• Core Architecture: CPLD
• Core Sub-architecture: MAX
• Silicon Core Number: 5M
• Silicon Family Name: MAX V
• Kit Contents: MAX V CPLD Development Board, USB Cable
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: 5M570ZF256
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2722

8–4
MAX V Device Handbook
Boundary-Scan Cells of a MAX V Device I/O Pin
Figure 8–3
Std. 1149.1 device.
Figure 8–3. Boundary-Scan Register
Except for the four JTAG pins and power pins, you can use all the pins of a MAX V
device (including clock pins) as user I/O pins and have a BSC. The 3-bit BSC consists
of a set of capture registers and a set of update registers. The capture registers can
connect to internal device data through the OUTJ and OEJ signals, while the update
registers connect to external data through the PIN_OUT and PIN_OE signals. The TAP
controller internally generates the SHIFT, CLOCK, and UPDATE global control signals for
the IEEE Std. 1149.1 BST registers; a decode of the instruction register generates the
MODE signal. The data signal path for the boundary-scan register runs from the serial
data in (SDI) signal to the serial data out (SDO) signal. The scan register begins at the
TDI pin and ends at the TDO pin of the device.
shows how test data is serially shifted around the periphery of the IEEE
TDI
TMS
TAP Controller
Internal Logic
TCK
Chapter 8: JTAG Boundary-Scan Testing in MAX V Devices
TDO
IEEE Std. 1149.1 Boundary-Scan Register
Each peripheral
element is either an
I/O pin, dedicated
input pin, or
dedicated
configuration pin.
December 2010 Altera Corporation