DK-DEV-5M570ZN Altera, DK-DEV-5M570ZN Datasheet - Page 133
![KIT DEV MAX V 5M570Z](/photos/18/31/183180/dk-dev-5m570zn_sml.jpg)
DK-DEV-5M570ZN
Manufacturer Part Number
DK-DEV-5M570ZN
Description
KIT DEV MAX V 5M570Z
Manufacturer
Altera
Series
MAX® Vr
Type
CPLDr
Datasheets
1.DK-DEV-5M570ZN.pdf
(30 pages)
2.DK-DEV-5M570ZN.pdf
(2 pages)
3.DK-DEV-5M570ZN.pdf
(30 pages)
4.DK-DEV-5M570ZN.pdf
(164 pages)
5.DK-DEV-5M570ZN.pdf
(24 pages)
Specifications of DK-DEV-5M570ZN
Contents
Board, Cable(s), Software and Documentation
Silicon Manufacturer
Altera
Core Architecture
CPLD
Core Sub-architecture
MAX
Silicon Core Number
5M
Silicon Family Name
MAX V
Kit Contents
MAX V CPLD Development Board, USB Cable
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
5M570ZF256
Lead Free Status / Rohs Status
Compliant
Other names
544-2722
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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- Download datasheet (5Mb)
Chapter 7: User Flash Memory in MAX V Devices
Software Support for UFM Block
January 2011 Altera Corporation
WREN (Write Enable)
The interface is powered-up in the write disable state. Therefore, WEN in the status
register (refer to
place, WREN must be issued to set WEN in the status register to 1. If the interface is in
read-only mode, WREN does not have any effect on WEN, because the status register does
not exist. After WEN is set to 1, it can be reset by the WRDI instruction; the WRITE and
SECTOR-ERASE instructions will not reset the WEN bit. WREN is issued through the
following sequence, as shown in
1. nCS is pulled low.
2. Opcode 00000110 is transmitted into the interface to set WEN to 1 in the status
3. After the transmission of the eighth bit of WREN, the interface is in wait state
4. nCS is pulled back to high.
Figure 7–28. WREN Operation Sequence
register.
(waiting for nCS to be pulled back to high). Any transmission after this is ignored.
Table
7–11) is 0 at power-up. Before any write is allowed to take
SCK
nCS
SI
SO
Figure
MSB
0
1
High Impedance
7–28:
Instruction
2
8-bit
06
3
H
4
5 6 7
MAX V Device Handbook
7–31
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