DK-DEV-5M570ZN Altera, DK-DEV-5M570ZN Datasheet - Page 157
![KIT DEV MAX V 5M570Z](/photos/18/31/183180/dk-dev-5m570zn_sml.jpg)
DK-DEV-5M570ZN
Manufacturer Part Number
DK-DEV-5M570ZN
Description
KIT DEV MAX V 5M570Z
Manufacturer
Altera
Series
MAX® Vr
Type
CPLDr
Datasheets
1.DK-DEV-5M570ZN.pdf
(30 pages)
2.DK-DEV-5M570ZN.pdf
(2 pages)
3.DK-DEV-5M570ZN.pdf
(30 pages)
4.DK-DEV-5M570ZN.pdf
(164 pages)
5.DK-DEV-5M570ZN.pdf
(24 pages)
Specifications of DK-DEV-5M570ZN
Contents
Board, Cable(s), Software and Documentation
Silicon Manufacturer
Altera
Core Architecture
CPLD
Core Sub-architecture
MAX
Silicon Core Number
5M
Silicon Family Name
MAX V
Kit Contents
MAX V CPLD Development Board, USB Cable
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
5M570ZF256
Lead Free Status / Rohs Status
Compliant
Other names
544-2722
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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- DK-DEV-5M570ZN PDF datasheet #5
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- Download datasheet (5Mb)
Chapter 8: JTAG Boundary-Scan Testing in MAX V Devices
IEEE Std. 1149.1 BST Operation Control
Figure 8–10. IEEE Std. 1149.1 BST EXTEST Mode
December 2010 Altera Corporation
Figure 8–10
OUTJ
OUTJ
OEJ
OEJ
INJ
INJ
SHIFT
SHIFT
SDI
SDI
shows the capture, shift, and update phases of EXTEST mode.
0
1
0
1
0
1
0
1
0
1
0
1
CLOCK
CLOCK
D
D
D
D
D
D
Output
Output
Input
Input
OE
OE
Q
Q
Q
Q
Q
Q
(Shift and Update Phase)
SDO
SDO
Capture
Registers
Capture
Registers
(Capture Phase)
UPDATE
UPDATE
D
D
D
D
Output
Output
OE
OE
Q
Q
Q
Q
Update
Registers
Update
Registers
HIGHZ
HIGHZ
0
1
0
1
MODE
MODE
0
1
0
1
0
1
0
1
Global Signals
Global Signals
PIN_IN
PIN_OE
PIN_OUT
PIN_IN
PIN_OE
PIN_OUT
Output
Buffer
Output
Buffer
Pin
Pin
MAX V Device Handbook
8–11
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