DK-DEV-5M570ZN Altera, DK-DEV-5M570ZN Datasheet - Page 111
![KIT DEV MAX V 5M570Z](/photos/18/31/183180/dk-dev-5m570zn_sml.jpg)
DK-DEV-5M570ZN
Manufacturer Part Number
DK-DEV-5M570ZN
Description
KIT DEV MAX V 5M570Z
Manufacturer
Altera
Series
MAX® Vr
Type
CPLDr
Datasheets
1.DK-DEV-5M570ZN.pdf
(30 pages)
2.DK-DEV-5M570ZN.pdf
(2 pages)
3.DK-DEV-5M570ZN.pdf
(30 pages)
4.DK-DEV-5M570ZN.pdf
(164 pages)
5.DK-DEV-5M570ZN.pdf
(24 pages)
Specifications of DK-DEV-5M570ZN
Contents
Board, Cable(s), Software and Documentation
Silicon Manufacturer
Altera
Core Architecture
CPLD
Core Sub-architecture
MAX
Silicon Core Number
5M
Silicon Family Name
MAX V
Kit Contents
MAX V CPLD Development Board, USB Cable
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
5M570ZF256
Lead Free Status / Rohs Status
Compliant
Other names
544-2722
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Chapter 7: User Flash Memory in MAX V Devices
UFM Operating Modes
January 2011 Altera Corporation
Read/Stream Read
The three control signals, PROGRAM, ERASE, and BUSY are not required during a read or
stream read operation. To perform a read operation, the address register must be
loaded with the reference address where the data is or is going to be located in the
UFM. The address register can be stopped from incrementing or shifting addresses
from ARDin by stopping the ARCLK clock pulse. DRSHFT must be asserted low at the next
rising edge of DRCLK to load the data from the UFM to the data register. To shift the bits
from the register, 16 clock pulses must be provided to read 16-bit wide data. You can
use DRCLK to control the read time or disable the data register by discontinuing the
DRCLK clock pulse.
The UFM block can also perform a stream read operation, using the address
increment feature to read continuously from the UFM. Stream read mode is started by
loading the base address into the address register. DRSHFT must then be asserted low at
the first rising edge of DRCLK to load data into the data register from the address
pointed to by the address register. DRSHFT will then assert high to shift out the 16-bit
wide data with the MSB out first.
during stream read mode.
Figure 7–5. UFM Read Waveforms
Figure 7–6. UFM Stream Read Waveforms
PROGRAM
PROGRAM
OSC_ENA
OSC_ENA
ARSHFT
DRSHFT
DRSHFT
ARSHFT
DRDout
DRDout
ARCLK
DRCLK
ERASE
DRCLK
ERASE
ARCLK
DRDin
ARDin
DRDin
ARDin
BUSY
BUSY
t
t
Figure 7–5
ASU
ADS
t
ACLK
9 Address Bits
9 Address Bits
shows the UFM control waveforms during read mode.
Figure 7–6
t
t
ADH
AH
t
DCO
t
Increment
DSS
Address
shows the UFM control waveforms
t
DCLK
16 Data Bits
16 Data Bits
t
DSH
MAX V Device Handbook
Increment
Address
7–9
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