DK-DEV-5M570ZN Altera, DK-DEV-5M570ZN Datasheet - Page 19
![KIT DEV MAX V 5M570Z](/photos/18/31/183180/dk-dev-5m570zn_sml.jpg)
DK-DEV-5M570ZN
Manufacturer Part Number
DK-DEV-5M570ZN
Description
KIT DEV MAX V 5M570Z
Manufacturer
Altera
Series
MAX® Vr
Type
CPLDr
Datasheets
1.DK-DEV-5M570ZN.pdf
(30 pages)
2.DK-DEV-5M570ZN.pdf
(2 pages)
3.DK-DEV-5M570ZN.pdf
(30 pages)
4.DK-DEV-5M570ZN.pdf
(164 pages)
5.DK-DEV-5M570ZN.pdf
(24 pages)
Specifications of DK-DEV-5M570ZN
Contents
Board, Cable(s), Software and Documentation
Silicon Manufacturer
Altera
Core Architecture
CPLD
Core Sub-architecture
MAX
Silicon Core Number
5M
Silicon Family Name
MAX V
Kit Contents
MAX V CPLD Development Board, USB Cable
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
5M570ZF256
Lead Free Status / Rohs Status
Compliant
Other names
544-2722
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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- DK-DEV-5M570ZN PDF datasheet #2
- DK-DEV-5M570ZN PDF datasheet #3
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- DK-DEV-5M570ZN PDF datasheet #5
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- Download datasheet (5Mb)
Chapter 2: MAX V Architecture
Logic Array Blocks
Figure 2–5. LAB-Wide Control Signals
December 2010 Altera Corporation
Dedicated
LAB Column
Clocks
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
With the LAB-wide addnsub control signal, a single LE can implement a one-bit adder
and subtractor. This signal saves LE resources and improves performance for logic
functions such as correlators and signed multipliers that alternate between addition
and subtraction depending on data.
The LAB column clocks [3..0], driven by the global clock network, and LAB local
interconnect generate the LAB-wide control signals. The MultiTrack interconnect
structure drives the LAB local interconnect for non-global control signal generation.
The MultiTrack interconnect’s inherent low skew allows clock and control signal
distribution in addition to data signals.
generation circuit.
4
labclk1
labclkena1
labclk2
labclkena2
Figure 2–5
asyncload
or labpre
syncload
shows the LAB control signal
labclr1
labclr2
MAX V Device Handbook
synclr
addnsub
2–7
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