DK-DEV-5M570ZN Altera, DK-DEV-5M570ZN Datasheet - Page 19

• Manufacturer Part Number: DK-DEV-5M570ZN
• Description: KIT DEV MAX V 5M570Z
• Manufacturer: Altera
• Series: MAX® Vr
• Type: CPLDr

Specifications of DK-DEV-5M570ZN

• Contents: Board, Cable(s), Software and Documentation
• Silicon Manufacturer: Altera
• Core Architecture: CPLD
• Core Sub-architecture: MAX
• Silicon Core Number: 5M
• Silicon Family Name: MAX V
• Kit Contents: MAX V CPLD Development Board, USB Cable
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: 5M570ZF256
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2722

Chapter 2: MAX V Architecture
Logic Array Blocks
Figure 2–5. LAB-Wide Control Signals
December 2010 Altera Corporation
Dedicated
LAB Column
Clocks
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
With the LAB-wide addnsub control signal, a single LE can implement a one-bit adder
and subtractor. This signal saves LE resources and improves performance for logic
functions such as correlators and signed multipliers that alternate between addition
and subtraction depending on data.
The LAB column clocks [3..0], driven by the global clock network, and LAB local
interconnect generate the LAB-wide control signals. The MultiTrack interconnect
structure drives the LAB local interconnect for non-global control signal generation.
The MultiTrack interconnect’s inherent low skew allows clock and control signal
distribution in addition to data signals.
generation circuit.
4
labclk1
labclkena1
labclk2
labclkena2
Figure 2–5
asyncload
or labpre
syncload
shows the LAB control signal
labclr1
labclr2
MAX V Device Handbook
synclr
addnsub
2–7