DK-DEV-5M570ZN Altera, DK-DEV-5M570ZN Datasheet - Page 68

• Manufacturer Part Number: DK-DEV-5M570ZN
• Description: KIT DEV MAX V 5M570Z
• Manufacturer: Altera
• Series: MAX® Vr
• Type: CPLDr

Specifications of DK-DEV-5M570ZN

• Contents: Board, Cable(s), Software and Documentation
• Silicon Manufacturer: Altera
• Core Architecture: CPLD
• Core Sub-architecture: MAX
• Silicon Core Number: 5M
• Silicon Family Name: MAX V
• Kit Contents: MAX V CPLD Development Board, USB Cable
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: 5M570ZF256
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2722

3–20
Table 3–27. Global Clock External I/O Timing Parameters for the 5M240Z Device
Table 3–28. Global Clock External I/O Timing Parameters for the 5M570Z Device
Table 3–29. Global Clock External I/O Timing Parameters for the 5M1270Z Device
MAX V Device Handbook
t
t
f
Notes to
(1) The maximum frequency is limited by the I/O standard on the clock input pin. The 16-bit counter critical delay performs faster than this global
(2) Only applicable to the T144 package of the 5M240Z device.
t
t
t
t
t
t
t
t
f
Note to
(1) The maximum frequency is limited by the I/O standard on the clock input pin. The 16-bit counter critical delay performs faster than this global
t
t
t
t
t
t
CL
CNT
CNT
PD1
PD2
SU
H
CO
CH
CL
CNT
CNT
PD1
PD2
SU
H
CO
CH
Symbol
Symbol
Symbol
clock input pin maximum frequency.
clock input pin maximum frequency.
Table
Table
Global clock low time
Minimum global clock period for 16-bit
counter
Maximum global clock frequency for 16-bit
counter
Worst case pin-to-pin delay through one LUT
Best case pin-to-pin delay through one LUT
Global clock setup time
Global clock hold time
Global clock to output delay
Global clock high time
Global clock low time
Minimum global clock period for 16-bit
counter
Maximum global clock frequency for 16-bit
counter
Worst case pin-to-pin delay through one LUT
Best case pin-to-pin delay through one LUT
Global clock setup time
Global clock hold time
Global clock to output delay
Global clock high time
3–28:
3–27:
Table 3–28
Table 3–29
Parameter
Parameter
Parameter
lists the external I/O timing parameters for the 5M570Z device.
lists the external I/O timing parameters for the 5M1270Z device.
Condition
Condition
Condition
10 pF
10 pF
10 pF
10 pF
10 pF
10 pF
—
—
—
—
—
—
—
—
—
—
—
—
Chapter 3: DC and Switching Characteristics for MAX V Devices
Min
253
Min
253
253
5.4
2.2
2.0
5.4
—
—
—
—
Min
0
216
2.0
1.5
—
—
0
C4
C4
C4
(Note
(Note 1)
184.1
184.1
(Note
Max
Max
9.5
5.7
6.7
—
—
—
—
—
—
—
Max
8.1
4.8
5.9
—
—
—
1),
1),
(2)
January 2011 Altera Corporation
(2)
Timing Model and Specifications
Min
339
Min
339
339
8.4
4.4
2.0
8.4
—
—
—
—
Min
0
266
1.9
2.0
—
—
(Part 1 of 2)
0
C5, I5
C5, I5
C5, I5
118.3
118.3
17.7
Max
Max
8.5
8.7
—
—
—
—
—
—
—
Max
10.0
5.9
7.3
—
—
—
MHz
MHz
Unit
Unit
ps
ns
ns
ns
ns
ns
ns
ps
ps
ns
Unit
ns
ns
ns
ns
ns
ps