DK-DEV-5M570ZN Altera, DK-DEV-5M570ZN Datasheet - Page 139

• Manufacturer Part Number: DK-DEV-5M570ZN
• Description: KIT DEV MAX V 5M570Z
• Manufacturer: Altera
• Series: MAX® Vr
• Type: CPLDr

Specifications of DK-DEV-5M570ZN

• Contents: Board, Cable(s), Software and Documentation
• Silicon Manufacturer: Altera
• Core Architecture: CPLD
• Core Sub-architecture: MAX
• Silicon Core Number: 5M
• Silicon Family Name: MAX V
• Kit Contents: MAX V CPLD Development Board, USB Cable
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: 5M570ZF256
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2722

Chapter 7: User Flash Memory in MAX V Devices
Software Support for UFM Block
Table 7–16. Parallel Interface Timing Parameters
January 2011 Altera Corporation
t
t
t
COMMAND
HNBUSY
HBUS
Symbol
The time required for the command signal (nREAD/nWRITE/nERASE)
to be asserted and held low to initiate a read/write/erase sequence
Maximum delay between command signal’s falling edge to the
nBUSY signal’s falling edge
The time that the data and address buses must be present at the
data input and address register ports after the command signal has
been asserted low
ALTUFM Parallel Interface Timing Specification
Figure 7–34
the parallel interface instruction signals. The nREAD, nWRITE, and nERASE signals are
active low signals.
Figure 7–34. Parallel Interface Timing Waveform
Instantiating Parallel Interface Using Quartus II ALTUFM_PARALLEL
Megafunction
Figure 7–35
interface instantiation in the Quartus II software.
Figure 7–35. ALTUFM_PARALLEL Megafunction Symbol for Parallel Interface Instantiation
Command
nBusy
Data or Address Bus
shows the timing specifications for the parallel interface.
shows the ALTUFM_PARALLEL megafunction symbol for a parallel
Description
t
HNBUSY
t
HBUS
t
COMMAND
Minimum (ns)
600
600
—
MAX V Device Handbook
Table 7–16
Maximum (ns)
3,000
300
—
lists
7–37