DK-DEV-5M570ZN Altera, DK-DEV-5M570ZN Datasheet - Page 118

• Manufacturer Part Number: DK-DEV-5M570ZN
• Description: KIT DEV MAX V 5M570Z
• Manufacturer: Altera
• Series: MAX® Vr
• Type: CPLDr

Specifications of DK-DEV-5M570ZN

• Contents: Board, Cable(s), Software and Documentation
• Silicon Manufacturer: Altera
• Core Architecture: CPLD
• Core Sub-architecture: MAX
• Silicon Core Number: 5M
• Silicon Family Name: MAX V
• Kit Contents: MAX V CPLD Development Board, USB Cable
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: 5M570ZF256
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2722

7–16
Figure 7–12. Byte Write Sequence
MAX V Device Handbook
S – Start Condition
P – Stop Condition
A – Acknowledge
S
Figure 7–11. Slave Address Bits
After the master sends a start condition and the slave address byte, the ALTUFM_I2C
logic monitors the bus and responds with an acknowledge (on the SDA line) when its
address matches the transmitted slave address. The ALTUFM_I2C megafunction then
performs a read or write operation to or from the UFM, depending on the state of the
bit.
Byte Write Operation
The master initiates a transfer by generating a start condition, then sending the correct
slave address (with the R/W bit set to 0) to the slave. If the slave address matches, the
ALTUFM_I2C slave acknowledges on the ninth clock pulse. The master then transfers
an 8-bit byte address to the UFM, which acknowledges the reception of the address.
The master transfers the 8-bit data to be written to the UFM. After the ALTUFM_I2C
logic acknowledges the reception of the 8-bit data, the master generates a stop
condition. The internal write from the MAX V logic array to the UFM begins only
after the master generates a stop condition. While the UFM internal write cycle is in
progress, the ALTUFM_I2C logic ignores any attempt made by the master to initiate a
new transfer.
Notes to
(1) For the 4-Kbit memory size, the A
(2) For the 8-Kbit memory size, the A
Slave Address
address.
the A
Figure
1
location in the slave address becomes the MSB (a9) of the memory byte address.
7–11:
Figure 7–12
"0" (write)
R/W
1- or 2-Kbit Memory Size
4-Kbit Memory Size (1)
8-Kbit Memory Size (2)
A
shows the byte write sequence.
0
0
location in the slave address becomes the MSB (a8) of the memory byte
location in the slave address becomes a8 of the memory byte address, while
Byte Address
MSB
MSB
MSB
1
1
1
0
0
0
A
1
1
1
Chapter 7: User Flash Memory in MAX V Devices
0
0
0
A
A
A
2
2
2
Data
A
A
a9
1
1
A
a8
a8
January 2011 Altera Corporation
0 R/W
Software Support for UFM Block
From Master to Slave
From Slave to Master
R/W
R/W
LSB
LSB
LSB
A
P