DK-DEV-5M570ZN Altera, DK-DEV-5M570ZN Datasheet - Page 31

• Manufacturer Part Number: DK-DEV-5M570ZN
• Description: KIT DEV MAX V 5M570Z
• Manufacturer: Altera
• Series: MAX® Vr
• Type: CPLDr

Specifications of DK-DEV-5M570ZN

• Contents: Board, Cable(s), Software and Documentation
• Silicon Manufacturer: Altera
• Core Architecture: CPLD
• Core Sub-architecture: MAX
• Silicon Core Number: 5M
• Silicon Family Name: MAX V
• Kit Contents: MAX V CPLD Development Board, USB Cable
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: 5M570ZF256
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2722

Chapter 2: MAX V Architecture
Global Signals
Global Signals
December 2010 Altera Corporation
Each MAX V device has four dual-purpose dedicated clock pins (GCLK[3..0], two
pins on the left side and two pins on the right side) that drive the global clock network
for clocking, as shown in
they are not used to drive the global clock network.
The four global clock lines in the global clock network drive throughout the entire
device. The global clock network can provide clocks for all resources within the
device including LEs, LAB local interconnect, IOEs, and the UFM block. The global
clock lines can also be used for global control signals, such as clock enables,
synchronous or asynchronous clears, presets, output enables, or protocol control
signals such as TRDY and IRDY for the PCI I/O standard. Internal logic can drive the
global clock network for internally-generated global clocks and control signals.
Figure 2–13
Figure 2–13. Global Clock Generation
Note to
(1) Any I/O pin can use a MultiTrack interconnect to route as a logic array-generated global clock signal.
The global clock network drives to individual LAB column signals, LAB column
clocks [3..0], that span an entire LAB column from the top to the bottom of the
device. Unused global clocks or control signals in an LAB column are turned off at the
LAB column clock buffers shown in
multiplexed down to two LAB clock signals and one LAB clear signal. Other control
signal types route from the global clock network into the LAB local interconnect. For
more information, refer to
Figure 2–13
shows the various sources that drive the global clock network.
:
Logic Array(1)
GCLK0
GCLK1
GCLK2
GCLK3
Figure
“LAB Control Signals” on page
2–13. These four pins can also be used as GPIOs if
4
Figure
2–14. The LAB column clocks [3..0] are
4
Global Clock
Network
2–6.
MAX V Device Handbook
2–19