DK-DEV-5M570ZN Altera, DK-DEV-5M570ZN Datasheet - Page 39

• Manufacturer Part Number: DK-DEV-5M570ZN
• Description: KIT DEV MAX V 5M570Z
• Manufacturer: Altera
• Series: MAX® Vr
• Type: CPLDr

Specifications of DK-DEV-5M570ZN

• Contents: Board, Cable(s), Software and Documentation
• Silicon Manufacturer: Altera
• Core Architecture: CPLD
• Core Sub-architecture: MAX
• Silicon Core Number: 5M
• Silicon Family Name: MAX V
• Kit Contents: MAX V CPLD Development Board, USB Cable
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: 5M570ZF256
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2722

Chapter 2: MAX V Architecture
I/O Structure
Figure 2–19. IOE Structure for MAX V Devices
Notes to
(1) Available only in I/O bank 3 of 5M1270Z and 5M2210Z devices.
(2) The programmable pull-up resistor is active during power-up, in-system programming (ISP), and if the device is unprogrammed.
December 2010 Altera Corporation
Figure
Fast I/O Connection
Data_in
2–19:
Fast_out
A dedicated fast I/O connection from the adjacent LAB to the IOEs within an I/O
block provides faster output delays for clock-to-output and t
This connection exists for data output signals, not output enable signals or input
signals.
Data_out
Figure
OE
2–20,
Figure
Drive Strength Control
Programmable
Input Delay
Open-Drain Output
DEV_OE
2–21, and
Slew Control
Optional Schmitt
Trigger Input
Figure 2–22
Optional
PCI Clamp (1)
V
CCIO
V
illustrate the fast I/O connection.
CCIO
I/O Pin
Programmable
Pull-Up (2)
PD
Optional Bus-Hold
Circuit
propagation delays.
MAX V Device Handbook
2–27