DK-DEV-5M570ZN Altera, DK-DEV-5M570ZN Datasheet - Page 134
![KIT DEV MAX V 5M570Z](/photos/18/31/183180/dk-dev-5m570zn_sml.jpg)
DK-DEV-5M570ZN
Manufacturer Part Number
DK-DEV-5M570ZN
Description
KIT DEV MAX V 5M570Z
Manufacturer
Altera
Series
MAX® Vr
Type
CPLDr
Datasheets
1.DK-DEV-5M570ZN.pdf
(30 pages)
2.DK-DEV-5M570ZN.pdf
(2 pages)
3.DK-DEV-5M570ZN.pdf
(30 pages)
4.DK-DEV-5M570ZN.pdf
(164 pages)
5.DK-DEV-5M570ZN.pdf
(24 pages)
Specifications of DK-DEV-5M570ZN
Contents
Board, Cable(s), Software and Documentation
Silicon Manufacturer
Altera
Core Architecture
CPLD
Core Sub-architecture
MAX
Silicon Core Number
5M
Silicon Family Name
MAX V
Kit Contents
MAX V CPLD Development Board, USB Cable
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
5M570ZF256
Lead Free Status / Rohs Status
Compliant
Other names
544-2722
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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7–32
MAX V Device Handbook
WRDI (Write Disable)
After the UFM is programmed, WRDI can be issued to set WEN back to 0, disabling WRITE
and preventing inadvertent writing to the UFM. WRDI is issued through the following
sequence, as shown in
1. nCS is pulled low.
2. Opcode 00000100 is transmitted to set WEN to 0 in the status register.
3. After the transmission of the eighth bit of WRDI, the interface is in wait state
4. nCS is pulled back to high.
Figure 7–29. WRDI Operation Sequence
(waiting for nCS to be pulled back to high). Any transmission after this is ignored.
Figure
SCK
nCS
SI
SO
7–29:
MSB
0
1
High Impedance
Instruction
2
8-bit
04
3
H
4
5 6 7
Chapter 7: User Flash Memory in MAX V Devices
January 2011 Altera Corporation
Software Support for UFM Block
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