DK-DEV-5M570ZN Altera, DK-DEV-5M570ZN Datasheet - Page 110

• Manufacturer Part Number: DK-DEV-5M570ZN
• Description: KIT DEV MAX V 5M570Z
• Manufacturer: Altera
• Series: MAX® Vr
• Type: CPLDr

Specifications of DK-DEV-5M570ZN

• Contents: Board, Cable(s), Software and Documentation
• Silicon Manufacturer: Altera
• Core Architecture: CPLD
• Core Sub-architecture: MAX
• Silicon Core Number: 5M
• Silicon Family Name: MAX V
• Kit Contents: MAX V CPLD Development Board, USB Cable
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: 5M570ZF256
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2722

7–8
UFM Operating Modes
MAX V Device Handbook
f
f
1
This megafunction is in the I/O folder on page 2a of the MegaWizard Plug-In
Manager. On page 3 of the MAX II/MAX V Oscillator megafunction, you have an
option to choose to simulate the OSC output port at its maximum or minimum
frequency during the design simulation. The frequency chosen is only used as a
timing parameter simulation and does not affect the real MAX V device OSC output
frequency.
There are three different modes for the UFM block:
■
■
■
During program mode, address and data can be loaded concurrently. You can
manipulate the UFM interface controls as necessary to implement the specific
protocol provided the UFM timing specifications are met.
Figure 7–8
For program mode
signals can be asserted anytime after the address register and data register have been
loaded. Do not assert the READ, PROGRAM, and ERASE signals or shift data and address
into the UFM after entering the real-time ISP mode. You can use the RTP_BUSY signal to
detect the beginning and end of real-time ISP operation and generate control logic to
stop all UFM port operations. This user-generated control logic is only necessary for
the ALTUFM_NONE megafunction, which provides no auto-generated logic. The
other interfaces for the ALTUFM megafunction (ALTUFM_PARALLEL,
ALTUFM_SPI, ALTUFM_I2C) contain control logic to automatically monitor the
RTP_BUSY signal and will cease operations to the UFM when a real-time ISP operation
is in progress.
You can program the UFM or CFM block independently without overwriting the
other block, which is not programmed. The Quartus II programmer provides the
options to program the UFM and CFM blocks individually or together (the entire
MAX V Device).
For guidelines about using ISP and real-time ISP while using the UFM block within
your design, refer to
For a complete description of the device architecture, and for the specific values of the
timing parameters listed in this chapter, refer to the
chapter.
Read/Stream Read
Program (Write)
Erase
show the control waveforms for accessing UFM in three different modes.
(Figure
AN 100: In-System Programmability
7–7) and erase mode
(Figure
Chapter 7: User Flash Memory in MAX V Devices
MAX V Device Architecture
Guidelines.
7–8), the PROGRAM and ERASE
Figure 7–5
January 2011 Altera Corporation
through
UFM Operating Modes