DK-DEV-5M570ZN Altera, DK-DEV-5M570ZN Datasheet - Page 24

• Manufacturer Part Number: DK-DEV-5M570ZN
• Description: KIT DEV MAX V 5M570Z
• Manufacturer: Altera
• Series: MAX® Vr
• Type: CPLDr

Specifications of DK-DEV-5M570ZN

• Contents: Board, Cable(s), Software and Documentation
• Silicon Manufacturer: Altera
• Core Architecture: CPLD
• Core Sub-architecture: MAX
• Silicon Core Number: 5M
• Silicon Family Name: MAX V
• Kit Contents: MAX V CPLD Development Board, USB Cable
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: 5M570ZF256
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2722

2–12
Figure 2–9. Carry-Select Chain
MAX V Device Handbook
LAB Carry-In
A1
B1
A2
B2
A3
B3
A4
B4
A6
B6
A7
B7
A8
B8
A9
B9
A10
B10
A5
B5
The speed advantage of the carry-select chain is in the parallel pre-computation of
carry chains. Because the LAB carry-in selects the precomputed carry chain, not every
LE is in the critical path. Only the propagation delays between LAB carry-in
generation (LE5 and LE10) are now part of the critical path. This feature allows the
MAX V architecture to implement high-speed counters, adders, multipliers, parity
functions, and comparators of arbitrary width.
Figure 2–9
portion of the LUT generates the sum of two bits using the input signals and the
appropriate carry-in bit; the sum is routed to the output of the LE. The register can be
bypassed for simple adders or used for accumulator functions. Another portion of the
LUT generates carry-out bits. An LAB-wide carry-in bit selects which chain is used for
the addition of given inputs. The carry-in signal for each chain, carry-in0 or
carry-in1, selects the carry-out to carry forward to the carry-in signal of the
next-higher-order bit. The final carry-out signal is routed to an LE, where it is fed to
local, row, or column interconnects.
LAB Carry-Out
0
0
LE0
LE1
LE2
LE3
LE4
LE5
LE6
LE7
LE8
LE9
1
1
Sum1
Sum2
Sum3
Sum4
Sum5
Sum6
Sum7
Sum8
Sum9
Sum10
shows the carry-select circuitry in an LAB for a 10-bit full adder. One
To top of adjacent LAB
LAB Carry-In
Carry-In0
Carry-In1
data1
data2
Carry-Out0
LUT
LUT
LUT
LUT
Carry-Out1
December 2010 Altera Corporation
Chapter 2: MAX V Architecture
Sum
Logic Elements