IPR-PCIE/1 Altera, IPR-PCIE/1 Datasheet - Page 101

• Manufacturer Part Number: IPR-PCIE/1
• Description: IP CORE Renewal Of IP-PCIE/1
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 5: IP Core Interfaces
Avalon-ST Interface
Table 5–4. 64-, 128-, or 256-Bit Avalon-ST TX Datapath (Part 5 of 5)
Figure 5–15. TX Credit Signal
December 2010 Altera Corporation
tx_cred_data_fc_cp
Notes to
(1) For all signals, <n> is the virtual channel number, which can be 0 or 1.
(2) To be Avalon-ST compliant, you must use a readyLatency of 1 or 2 for hard IP implementation, and a readyLatency of 1 or 2 or 3 for the
(3) For the completion header, posted header, non-posted header, and non-posted data fields, a value of 7 indicates 7 or more available
(4) These signals only apply to hard IP implementations in Stratix IV GX, HardCopy IV GX, and Arria II GX devices.
(5) In Stratix IV, HardCopy, and Arria II GX hard IP implementations, the non-posted TLP credit field is valid for systems that support more than 1
(6) These signals apply only the Stratix IV, HardCopy, and Arria II GX hard IP implementations.
35
Notes to
(1) When infinite credits are available, the corresponding credit field is all 1's.
Completion Data
soft IP implementation. To facilitate timing closure, Altera recommends that you register both the tx_st_ready and tx_st_valid signals. If
no other delays are added to the ready-valid latency, this corresponds to a readyLatency of 2.
credits.
NP credit. In systems that allocate only 1 NP credit, the receipt of completions should be used to detect the credit release.
Table
Figure
Mapping of Avalon-ST Packets to PCI Express
(1)
Signal
5–4:
f
5–15:
24
Figure 5–15
non-posted header, non-posted data and posted header fields, a saturation value of
seven indicates seven or more available transmit credits.
For the hard IP implementation in Arria II GX, HardCopy IV GX, and Stratix IV GX
devices, a saturation value of six or greater should be used for non-posted header and
non-posted data. If your system allocates a single non-posted credit, you can use the
receipt of completions to detect the release of credit for non-posted writes.
Figure 5–16–Figure 5–25
Express TLPs. These mappings apply to all types of TLPs, including posted,
non-posted and completion. Message TLPs use the mappings shown for four dword
headers. TLP data is always address-aligned on the Avalon-ST interface whether or
not the lower dwords of the header contains a valid address as may be the case with
TLP type (message request with data payload).
For additional information about TLP packet headers, refer to
Transaction Layer Packet (TLP) Header Formats
Header Fields in the
23
Comp Hdr
12
Width Dir
illustrates the TLP fields of the tx_cred bus. For completion header,
21 20
NPData
O
PCI Express Base Specification
18 17
component
specific
Avalon-ST
illustrate the mappings between Avalon-ST packets and PCI
Type
NP Hdr
15 14
Data credit limit for the received FC completions. Each
credit is 16 bytes.
Posted Data
2.0.
and Section 2.2.1 Common Packet
Description
PCI Express Compiler User Guide
Appendix A,
3 2
Posted
Header
(1)
5–17
0