IPR-PCIE/1 Altera, IPR-PCIE/1 Datasheet - Page 146

• Manufacturer Part Number: IPR-PCIE/1
• Description: IP CORE Renewal Of IP-PCIE/1
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

6–2
Table 6–1. Common Configuration Space Header (Part 2 of 2)
Table 6–2. PCI Type 0 Configuration Space Header (Endpoints), Rev2 Spec: Type 0 Configuration Space Header
PCI Express Compiler User Guide
0x2C0:0x2FC
0x300:0x33C
0x340:0x37C
0x380:0x3BC
0x3C0:0x3FC
0x400:0x7FC
0x800:0x834
0x838:0xFFF
0x000
0x004
0x008
0x00C
0x010
0x014
0x018
0x01C
0x020
0x024
0x028
0x02C
0x030
0x034
0x038
0x03C
Note to
(1) Refer to
Byte Offset
Byte Offset
Base Specification 2.0.
Table
Table 6–23 on page 6–12
6–2:
1
BAR Table (BAR0)
BAR Table (BAR1)
BAR Table (BAR2)
BAR Table (BAR3)
BAR Table (BAR4)
BAR Table (BAR5)
Expansion ROM base address
Reserved
Reserved
Reserved
Implement advanced error reporting
Reserved
Port VC3 arbitration table (Reserved)
Port VC4 arbitration table (Reserved)
Port VC5 arbitration table (Reserved)
Port VC6 arbitration table (Reserved)
Port VC7 arbitration table (Reserved)
Table 6–2
In the following tables, the names of fields that are defined by parameters in the
parameter editor are links to the description of that parameter. These links appear as
green
text.
31:24
0x00
31:24
0x00
for a comprehensive list of correspondences between the configuration space registers and the
describes the type 0 configuration settings.
Subsystem ID
Device ID
Status
Header Type
(Port
Class code
23:16
0x00
23:16
(optional)
type)
Reserved
Interrupt Pin
0x00
15:8
15:8
Subsystem vendor ID
Configuration Space Register Content
Vendor ID
December 2010 Altera Corporation
Command
Chapter 6: Register Descriptions
Cache Line Size
Capabilities Pointer
Interrupt Line
Revision ID
7:0
7:0
PCI Express